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Low Complexity Deep Learning Augmented Wireless Channel Estimation for Pilot-Based OFDM on Zynq System on Chip

Animesh Sharma, Syed Asrar Ul Haq, Sumit J. Darak

TL;DR

A novel compute-efficient LS-augmented interpolated deep neural network (LSiDNN) based CE algorithm is proposed and realized on ZSoC, validating the superiority of DL-based CE and LMMSE over LS for various signal-to-noise ratios (SNR) and wireless channels in terms of mean square error (MSE) and bit error rate (BER).

Abstract

Channel estimation (CE) is one of the critical signal-processing tasks of the wireless physical layer (PHY). Recent deep learning (DL) based CE have outperformed statistical approaches such as least-square-based CE (LS) and linear minimum mean square error-based CE (LMMSE). However, existing CE approaches have not yet been realized on system-on-chip (SoC). The first contribution of this paper is to efficiently implement the existing state-of-the-art CE algorithms on Zynq SoC (ZSoC), comprising of ARM processor and field programmable gate array (FPGA), via hardware-software co-design and fixed point analysis. We validate the superiority of DL-based CE and LMMSE over LS for various signal-to-noise ratios (SNR) and wireless channels in terms of mean square error (MSE) and bit error rate (BER). We also highlight the high complexity, execution time, and power consumption of DL-based CE and LMMSE approaches. To address this, we propose a novel compute-efficient LS-augmented interpolated deep neural network (LSiDNN) based CE algorithm and realize it on ZSoC. The proposed LSiDNN offers 88-90% lower execution time and 38-85% lower resource utilization than state-of-the-art DL-based CE for identical MSE and BER. LSiDNN offers significantly lower MSE and BER than LMMSE, and the gain improves with increased mobility between transceivers. It offers 75% lower execution time and 90-94% lower resource utilization than LMMSE.

Low Complexity Deep Learning Augmented Wireless Channel Estimation for Pilot-Based OFDM on Zynq System on Chip

TL;DR

A novel compute-efficient LS-augmented interpolated deep neural network (LSiDNN) based CE algorithm is proposed and realized on ZSoC, validating the superiority of DL-based CE and LMMSE over LS for various signal-to-noise ratios (SNR) and wireless channels in terms of mean square error (MSE) and bit error rate (BER).

Abstract

Channel estimation (CE) is one of the critical signal-processing tasks of the wireless physical layer (PHY). Recent deep learning (DL) based CE have outperformed statistical approaches such as least-square-based CE (LS) and linear minimum mean square error-based CE (LMMSE). However, existing CE approaches have not yet been realized on system-on-chip (SoC). The first contribution of this paper is to efficiently implement the existing state-of-the-art CE algorithms on Zynq SoC (ZSoC), comprising of ARM processor and field programmable gate array (FPGA), via hardware-software co-design and fixed point analysis. We validate the superiority of DL-based CE and LMMSE over LS for various signal-to-noise ratios (SNR) and wireless channels in terms of mean square error (MSE) and bit error rate (BER). We also highlight the high complexity, execution time, and power consumption of DL-based CE and LMMSE approaches. To address this, we propose a novel compute-efficient LS-augmented interpolated deep neural network (LSiDNN) based CE algorithm and realize it on ZSoC. The proposed LSiDNN offers 88-90% lower execution time and 38-85% lower resource utilization than state-of-the-art DL-based CE for identical MSE and BER. LSiDNN offers significantly lower MSE and BER than LMMSE, and the gain improves with increased mobility between transceivers. It offers 75% lower execution time and 90-94% lower resource utilization than LMMSE.
Paper Structure (27 sections, 8 equations, 23 figures, 10 tables)

This paper contains 27 sections, 8 equations, 23 figures, 10 tables.

Table of Contents

  1. Introduction
  2. System Model
  3. State-of-the-art DL-based CE
  4. ChannelNet
  5. ReEsNet
  6. iResNet
  7. Proposed DL-Augmented Channel Estimation
  8. Proposed LSiDNN
  9. Performance and Complexity Analysis for Software Realizations Using Floating Point Arithmetic
  10. Theoretical Complexity Analysis
  11. Algorithms to Architecture Mapping of CE on SoC
  12. Conventional Channel Estimation
  13. Proposed IReSNet Hardware Architecture
  14. Proposed LSiDNN Architecture
  15. Performance and Complexity Analysis on SoC
  16. ...and 12 more sections

Figures (23)

  • Figure 1: Block diagram of an OFDM-based transceiver PHY.
  • Figure 2: OFDM frame consisting of pilot and data sub-carriers.
  • Figure 3: Illustrative example of bilinear interpolation.
  • Figure 4: DL-based channel estimation.
  • Figure 5: ChannelNet architecture in channelNet for channel estimation.
  • ...and 18 more figures