Quantum Hardware Roofline: Evaluating the Impact of Gate Expressivity on Quantum Processor Design

TL;DR

The criteria for gate design and selection is extended from only maximizing average fidelity to a more comprehensive approach that additionally considers expressivity with respect to algorithm structures and emphasizes the importance of hardware-software codesign for quantum computing.

Abstract

The design space of current quantum computers is expansive with no obvious winning solution. This leaves practitioners with a clear question: "What is the optimal system configuration to run an algorithm?". This paper explores hardware design trade-offs across NISQ systems to guide algorithm and hardware design choices. The evaluation is driven by algorithmic workloads and algorithm fidelity models which capture architectural features such as gate expressivity, fidelity, and crosstalk. We also argue that the criteria for gate design and selection should be extended from maximizing average fidelity to a more comprehensive approach that takes into account the gate expressivity with respect to algorithmic structures. We consider native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, $\sqrt{\text{iSWAP}}$), proposed gates (B Gate, $\sqrt[4]{\text{CNOT}}$, $\sqrt[8]{\text{CNOT}}$), as well as parameterized gates (FSim, XY). Our methodology is driven by a custom synthesis driven circuit compilation workflow, which is able to produce minimal circuit representations for a given system configuration. By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software co-design for quantum computing.

Figures (15)

• Figure 1: Our Hardware Comparison Procedure: A synthesis-based cross-compilation process (sometimes called "transpilation") allows us to explore multiple gate sets and there ability to express an algorithm in terms of gate count, depth, and parallelism. From there, we can understand the effects of topology and fidelity on the overall performance of a quantum machine.
• Figure 2: Normalized two-qubit gate count for existing hardware (top) and theorized hardware (bottom). We plot the relative count with respect to the best attainable CNOT based circuit (best optimization across compilers). This shows the gate count when using the logical algorithm connectivity, which correlates to the gate's respective ability to represent the algorithm.
• Figure 3: Validation experiments for our fidelity model. (a) Plot against full simulation on IBM Noisy Simulator and derived depolarization channel. We keep constant depth circuits with varied CNOT count gates. (b) Fidelity plot of constant count circuits as we vary circuit depth. (c) Varying the 1-qubit gate error of our model vs. a general depolarization model. (d) Varying the 2-qubit gate error of our model vs. a general depolarization model.
• Figure 4: Machine capability to execute the adder_9 algorithm. CNOT fidelity is on the x-axis and the relative Sycamore fidelity on the y-axis. We plot the winning machine at each point. The middle area shows where the choice of best machine is a function of the single-qubit fidelity. In the other areas, each machine wins irrespective of 1-qubit gate fidelity. The published 2-qubit gate fidelities are shown with the black dotted lines: interestingly the CNOT based system is better, despite the better Sycamore gate fidelity.
• Figure 5: Gate set comparison against CNOT. CNOT fidelity fixed to the IBM Falcon. Each configuration can be improved by tuning the 2-qubit gates. Encouragingly, low entanglement gates $\sqrt[8]{CNOT}$ can provide better overall circuit fidelity for some algorithms. The bars correspond to the circuit families: TFIM, QAE, QFT, QAOA, QPE, Adders, Grover, Shor, Hubbard, QML, and VQE.

Theorems & Definitions (2)

• Definition 1: Digital Fidelity Model
• Definition 2: Cyclic Fidelity Model