Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis

TL;DR

This work addresses the data-movement bottleneck in processor-centric systems by evaluating Processing-Using-DRAM (PuD) on unmodified COTS DDR4 DRAM chips. The authors introduce a bulk in-DRAM computation approach based on simultaneous activation of neighboring subarrays to realize a functionally complete Boolean set (NOT, NAND, NOR) and many-input operations (up to 16 inputs for AND/OR/NAND/NOR), supported by two hypotheses about the underlying DRAM row-decoder and sense-amplifier behavior. Through an extensive study of 256 DRAM chips from SK Hynix and Samsung across densities, die revisions, and temperatures, they report high average success rates (e.g., NOT at 98.37% with 1 destination row; 16-input NAND/NOR/AND/OR around 94.9–95.9%), and show modest impact from data patterns, with stronger resilience to temperature changes. The work also reveals practical variability across devices and conditions (row distances to sense amplifiers, DRAM speed, and chip characteristics), and it provides open-source infrastructure for reproducibility and further exploration. Overall, the results establish DRAM as a viable computation substrate for bulk bitwise operations, potentially enabling significant reductions in data movement and energy in memory-centric systems.

Abstract

Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the potential to reduce or eliminate costly data movement between processing elements and main memory. Prior works experimentally demonstrate three-input MAJ (MAJ3) and two-input AND and OR operations in commercial off-the-shelf (COTS) DRAM chips. Yet, demonstrations on COTS DRAM chips do not provide a functionally complete set of operations. We experimentally demonstrate that COTS DRAM chips are capable of performing 1) functionally-complete Boolean operations: NOT, NAND, and NOR and 2) many-input (i.e., more than two-input) AND and OR operations. We present an extensive characterization of new bulk bitwise operations in 256 off-the-shelf modern DDR4 DRAM chips. We evaluate the reliability of these operations using a metric called success rate: the fraction of correctly performed bitwise operations. Among our 19 new observations, we highlight four major results. First, we can perform the NOT operation on COTS DRAM chips with a 98.37% success rate on average. Second, we can perform up to 16-input NAND, NOR, AND, and OR operations on COTS DRAM chips with high reliability (e.g., 16-input NAND, NOR, AND, and OR with an average success rate of 94.94%, 95.87%, 94.94%, and 95.85%, respectively). Third, data pattern only slightly affects bitwise operations. Our results show that executing NAND, NOR, AND, and OR operations with random data patterns decreases the success rate compared to all logic-1/logic-0 patterns by 1.39%, 1.97%, 1.43%, and 1.98%, respectively. Fourth, bitwise operations are highly resilient to temperature changes, with small success rate fluctuations of at most 1.66% when the temperature is increased from 50C to 95C. We open-source our infrastructure at https://github.com/CMU-SAFARI/FCDRAM

Figures (21)

• Figure 1: Demonstration of how modern DRAM can provide the NOT operation (a) and two-input AND and NAND operations (b).
• Figure 2: Bank and subarray organization in a DRAM chip.
• Figure 3: Command sequence for activating a DRAM row and the state of a DRAM cell during each related step.
• Figure 4: Our DRAM Bender based experimental setup.
• Figure 5: Coverage of each N$_{\texttt{RF}}$:N$_{\texttt{RL}}$ activation type across tested R$_{\texttt{F}}$ and R$_{\texttt{L}}$ row pairs.