PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators

TL;DR

The paper tackles the challenge of evaluating PIM accelerators for DNN inference while decoupling software and hardware design. It introduces an ISA-based framework comprising an ISA, a compiler with two mapping strategies, and a cycle-accurate SystemC simulator to model crossbar-based PIM hardware. Key contributions include enabling independent exploration of software optimizations and hardware configurations, and providing a detailed comparison with MNSIM2.0 to reveal the impact of realistic communication modeling on latency and energy. The results show that communication costs can dominate inference latency and that the framework enables systematic design-space exploration; the open-source release invites broader validation and usage.

Abstract

Processing-in-memory (PIM) has shown extraordinary potential in accelerating neural networks. To evaluate the performance of PIM accelerators, we present an ISA-based simulation framework including a dedicated ISA targeting neural networks running on PIM architectures, a compiler, and a cycleaccurate configurable simulator. Compared with prior works, this work decouples software algorithms and hardware architectures through the proposed ISA, providing a more convenient way to evaluate the effectiveness of software/hardware optimizations. The simulator adopts an event-driven simulation approach and has better support for hardware parallelism. The framework is open-sourced at https://github.com/wangxy-2000/pimsim-nn.

Figures (5)

• Figure 1: Workflow of the simulation framework.
• Figure 2: Accelerator architecture.
• Figure 3: Comparison of mapping algorithms.
• Figure 4: Latency results with different ROB sizes.
• Figure 5: Latency comparison with MNSIM2.0.