SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm

TL;DR

The paper tackles the prohibitive cost of exhaustive SEE evaluation in modern SoCs by introducing SSRESF, a framework that fuses clustering-based gate-level netlist analysis, SET/SEU fault models, and SVM-driven classification of sensitive circuit nodes to enable fast, automated soft-error analysis across the software stack. It builds a gate-level fault-injection pipeline using standard simulators and VPI interfaces, and constructs databases for SEU/SET across LET values, enabling targeted fault injection and SER estimation at the cluster level. A two-stage workflow combines clustering (to reduce sample space) with ML-based sensitivity prediction, achieving up to 12.78× speed-up with an average accuracy of 94.58% on 10 gate-level PULP SoC nets and revealing that buses and memories dominate SER while increasing bus width and system complexity raises risk. The results demonstrate practical viability for scalable radiation-resilience assessment and design-space exploration in contemporary SoCs, with clear guidance for targeted hardening of sensitive nodes.

Abstract

The ever-expanding scale of integrated circuits has brought about a significant rise in the design risks associated with radiation-resistant integrated circuit chips. Traditional single-particle experimental methods, with their iterative design approach, are increasingly ill-suited for the challenges posed by large-scale integrated circuits. In response, this article introduces a novel sensitivity-aware single-particle radiation effects simulation framework tailored for System-on-Chip platforms. Based on SVM algorithm we have implemented fast finding and classification of sensitive circuit nodes. Additionally, the methodology automates soft error analysis across the entire software stack. The study includes practical experiments focusing on RISC-V architecture, encompassing core components, buses, and memory systems. It culminates in the establishment of databases for Single Event Upsets (SEU) and Single Event Transients (SET), showcasing the practical efficacy of the proposed methodology in addressing radiation-induced challenges at the scale of contemporary integrated circuits. Experimental results have shown up to 12.78X speed-up on the basis of achieving 94.58% accuracy.

Figures (7)

• Figure 1: The overview of the SSRESF framework.
• Figure 2: The SET and SEU single-particle fault models.
• Figure 3: The SET and SEU single-particle soft error database.
• Figure 4: The classification process for sensitive circuit nodes.
• Figure 5: The features selection of SVM model.