Real-Time FPGA Demonstrator of ANN-Based Equalization for Optical Communications
Jonas Ney, Patrick Matalla, Vincent Lauinger, Laurent Schmalen, Sebastian Randel, Norbert Wehn
TL;DR
The paper tackles the challenge of achieving real-time, high-throughput ANN-based equalization in short-reach optical links where nonlinear impairments limit performance. It proposes a CNN-based equalizer tailored for FPGA implementation, featuring 3 conv layers with kernel size 9, batch normalization and ReLU in the first two layers, and aggressive parallelism to process 8 symbols per run, selected via design-space exploration to deliver about a 10× BER improvement over a linear equalizer at equivalent complexity. The FPGA implementation uses fixed-point arithmetic, AXI-Stream I/O, and a pipelined, multi-instance architecture to meet 30 Gbd throughput, demonstrated on a 20.56 km SSMF link with real-time DSP and BER visualization. The work provides a practical demonstration of ANN-based equalization in high-throughput optical systems and establishes a platform for visualizing and extending the approach, including avenues for unsupervised training and integration with prior FPGA-based demonstrations.
Abstract
In this work, we present a high-throughput field programmable gate array (FPGA) demonstrator of an artificial neural network (ANN)-based equalizer. The equalization is performed and illustrated in real-time for a 30 GBd, two-level pulse amplitude modulation (PAM2) optical communication system.