Toward High Performance, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ

TL;DR

This work proposes an energy-efficient non-von-Neumann in-pixel processing solution for neuromorphic vision sensors employing emerging (X) magnetic domain wall magnetic tunnel junction (MDWMTJ) for the first time, in conjunction with CMOS-based neuromorphic pixels.

Abstract

The desire to empower resource-limited edge devices with computer vision (CV) must overcome the high energy consumption of collecting and processing vast sensory data. To address the challenge, this work proposes an energy-efficient non-von-Neumann in-pixel processing solution for neuromorphic vision sensors employing emerging (X) magnetic domain wall magnetic tunnel junction (MDWMTJ) for the first time, in conjunction with CMOS-based neuromorphic pixels. Our hybrid CMOS+X approach performs in-situ massively parallel asynchronous analog convolution, exhibiting low power consumption and high accuracy across various CV applications by leveraging the non-volatility and programmability of the MDWMTJ. Moreover, our developed device-circuit-algorithm co-design framework captures device constraints (low tunnel-magnetoresistance, low dynamic range) and circuit constraints (non-linearity, process variation, area consideration) based on monte-carlo simulations and device parameters utilizing GF22nm FD-SOI technology. Our experimental results suggest we can achieve an average of 45.3% reduction in backend-processor energy, maintaining similar front-end energy compared to the state-of-the-art and high accuracy of 79.17% and 95.99% on the DVS-CIFAR10 and IBM DVS128-Gesture datasets, respectively.

Figures (7)

• Figure 1: (a) Device structures for SOT-based MDWMTJ. l_FL t_FL denote the length and thickness of the FL, t_OX and t_HM represent the thickness of the oxide and HM layer, respectively. R_P, R_AP, and R_N denote the MTJ resistance of the parallel, and-parallel and perpendicular state. (b) DW velocity as a function of the write current. (c) MTJ resistance as a function of applied voltage. (d) Effective MDWMTJ resistance as a function of the DW position.
• Figure 2: (a) The representative 3D heterogeneously integrated CMOS+X P^2M architecture utilizing Cu-Cu hybrid bonding, where the top die is backside illuminated CIS substrate, and the bottom die consists of P^2M compute elements. (b) A computing architecture of the MAC and thresholding operation considering a kernel size of 33.
• Figure 3: Embedded in-situ multi-bit (a) CMOS-based, (b) MDWMTJ-based, and (c) CMOS+X-based weight implementation. Transistors MW_x,y, MDWMTJs XW_x,y and transistors MW_x,y + MDWMTJs XW_x,y represent the weights in (a), (b), and (c), respectively, where, (x,y) = (1,1), (1,2), ... (3,3), considering a kernel size of 33.
• Figure 4: 1000 monte-carlo simulations of a random convolution operation with output activation spike simulated on GF 22nm FD-SOI node.
• Figure 5: Weight and threshold voltage reprogrammability simulation for two different applications.