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Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization

David Cuesta, José L. Risco-Martín, José L. Ayala, J. Ignacio Hidalgo

TL;DR

This work tackles heat and reliability challenges in 3D ICs by proposing a thermal-aware floorplanning framework that jointly optimizes functional-unit and TSV placement, liquid microchannels, and air isolation channels. The design flow combines three evolutionary algorithms (MfaFu, MfaTsv, and their variants) with an accurate thermal model to minimize constraint violations, interconnect length, and the maximum chip temperature $F_3$. Key contributions include TSV-aware placement, a feasibility-enhanced variant, and two cooling-domain strategies (liquid channels and air isolation) that reduce cooling costs while maintaining or improving thermal performance. Experimental validation on Niagara-based many-core architectures demonstrates up to about 37–57 K reductions in maximum temperature and substantial reductions in cooling-channel requirements when air isolation is employed, underscoring the practical impact for scalable 3D integration.

Abstract

3D stacked technology has emerged as an effective mechanism to overcome physical limits and communication delays found in 2D integration. However, 3D technology also presents several drawbacks that prevent its smooth application. Two of the major concerns are heat reduction and power density distribution. In our work, we propose a novel 3D thermal-aware floorplanner that includes: (1) an effective thermal-aware process with 3 different evolutionary algorithms that aim to solve the soft computing problem of optimizing the placement of functional units and through silicon vias, as well as the smooth inclusion of active cooling systems and new design strategies,(2) an approximated thermal model inside the optimization loop, (3) an optimizer for active cooling (liquid channels), and (4) a novel technique based on air channel placement designed to isolate thermal domains have been also proposed. The experimental work is conducted for a realistic many-core single-chip architecture based on the Niagara design. Results show promising improvements of the thermal and reliability metrics, and also show optimal scaling capabilities to target future-trend many-core systems.

Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization

TL;DR

This work tackles heat and reliability challenges in 3D ICs by proposing a thermal-aware floorplanning framework that jointly optimizes functional-unit and TSV placement, liquid microchannels, and air isolation channels. The design flow combines three evolutionary algorithms (MfaFu, MfaTsv, and their variants) with an accurate thermal model to minimize constraint violations, interconnect length, and the maximum chip temperature . Key contributions include TSV-aware placement, a feasibility-enhanced variant, and two cooling-domain strategies (liquid channels and air isolation) that reduce cooling costs while maintaining or improving thermal performance. Experimental validation on Niagara-based many-core architectures demonstrates up to about 37–57 K reductions in maximum temperature and substantial reductions in cooling-channel requirements when air isolation is employed, underscoring the practical impact for scalable 3D integration.

Abstract

3D stacked technology has emerged as an effective mechanism to overcome physical limits and communication delays found in 2D integration. However, 3D technology also presents several drawbacks that prevent its smooth application. Two of the major concerns are heat reduction and power density distribution. In our work, we propose a novel 3D thermal-aware floorplanner that includes: (1) an effective thermal-aware process with 3 different evolutionary algorithms that aim to solve the soft computing problem of optimizing the placement of functional units and through silicon vias, as well as the smooth inclusion of active cooling systems and new design strategies,(2) an approximated thermal model inside the optimization loop, (3) an optimizer for active cooling (liquid channels), and (4) a novel technique based on air channel placement designed to isolate thermal domains have been also proposed. The experimental work is conducted for a realistic many-core single-chip architecture based on the Niagara design. Results show promising improvements of the thermal and reliability metrics, and also show optimal scaling capabilities to target future-trend many-core systems.
Paper Structure (14 sections, 4 equations, 15 figures, 6 tables, 4 algorithms)

This paper contains 14 sections, 4 equations, 15 figures, 6 tables, 4 algorithms.

Table of Contents

  1. Introduction
  2. Thermal model
  3. Design Flow: Multi-objective Floorplanning Algorithm
  4. $_{\mathrm{}}$
  5. Optimization: $_{\mathrm{}}$
  6. $_{\mathrm{*}}$
  7. Liquid Channel Optimization: $_{\mathrm{}}$
  8. Air Isolation Placement Optimization: $_{\mathrm{}}$
  9. Experimental set-up
  10. Results
  11. Functional units and placement: $_{\mathrm{*}}$ + $_{\mathrm{}}$
  12. Liquid microchannel optimization: $_{\mathrm{}}$
  13. Air channel isolation: $_\mathrm{}$
  14. Conclusions

Figures (15)

  • Figure 1: 3D architectural concept
  • Figure 2: 3D design flow
  • Figure 3: Material cells: \ref{['fig:RegularCell']} Diffusive cell (silicon, silicon dioxide, air) and \ref{['fig:LiquidCell']} Liquid cell.
  • Figure 4: $_{\mathrm{}}$ A chromosome representing a solution of a platform with 4 cores, $C_i$, and 4 memories, $M_i$, \ref{['fig:ChromosomeFU']}, as well as crossover operation \ref{['fig:CrossoverFU']} and the two ways of mutation operator; swapping (up) and rotation of a FU (down) \ref{['fig:MutationFU']} operators.
  • Figure 5: Chromosome description.
  • ...and 10 more figures