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DDC: A Vision for a Disaggregated Datacenter

Mohammad Ewais, Paul Chow

TL;DR

This paper addresses persistent resource under-utilization in modern datacenters by advocating memory disaggregation as a resource-centric alternative to server-centric designs. It argues for a hardware-based pool architecture and a top-down design methodology inspired by traditional computer architecture, outlining compute nodes, caching, memory nodes, interconnects, storage, and management. It provides a structured analysis of state-of-the-art approaches, identifies design challenges, and proposes a research platform and prototyping path (simulators and FPGA-based systems) to enable quantitative comparisons. The proposed framework aims to improve utilization, reduce power waste, and enable scalable, fault-tolerant datacenters through a unified memory hierarchy and programmable memory/networking components.

Abstract

Datacenters of today have maintained the same architecture for decades using the server as the primary building block. However, this traditional approach suffers from under-utilization of its resources, often caused by over-allocating these resources when deploying applications to accommodate worst-case scenarios. Specifically, servers can quickly drain their over-allocated memory resources while their CPUs are not fully utilized. This problem gives rise to a different school of thought, where resources are disaggregated instead of tightly bound to servers. This can address the utilization problem by allowing each type of resource to be allocated, utilized and freed separately as required. New high performance communication protocols, like CXL, could pave the way for practical implementations of resource disaggregation. In this article, we argue it is time to reconsider the datacenter architecture as a whole. We present our vision for a disaggregated datacenter aided by well-established computer architecture design methodologies.

DDC: A Vision for a Disaggregated Datacenter

TL;DR

This paper addresses persistent resource under-utilization in modern datacenters by advocating memory disaggregation as a resource-centric alternative to server-centric designs. It argues for a hardware-based pool architecture and a top-down design methodology inspired by traditional computer architecture, outlining compute nodes, caching, memory nodes, interconnects, storage, and management. It provides a structured analysis of state-of-the-art approaches, identifies design challenges, and proposes a research platform and prototyping path (simulators and FPGA-based systems) to enable quantitative comparisons. The proposed framework aims to improve utilization, reduce power waste, and enable scalable, fault-tolerant datacenters through a unified memory hierarchy and programmable memory/networking components.

Abstract

Datacenters of today have maintained the same architecture for decades using the server as the primary building block. However, this traditional approach suffers from under-utilization of its resources, often caused by over-allocating these resources when deploying applications to accommodate worst-case scenarios. Specifically, servers can quickly drain their over-allocated memory resources while their CPUs are not fully utilized. This problem gives rise to a different school of thought, where resources are disaggregated instead of tightly bound to servers. This can address the utilization problem by allowing each type of resource to be allocated, utilized and freed separately as required. New high performance communication protocols, like CXL, could pave the way for practical implementations of resource disaggregation. In this article, we argue it is time to reconsider the datacenter architecture as a whole. We present our vision for a disaggregated datacenter aided by well-established computer architecture design methodologies.
Paper Structure (16 sections, 3 figures)

This paper contains 16 sections, 3 figures.

Table of Contents

  1. STATE OF THE ART
  2. Limitations
  3. INSIGHT: REUSE THE WHEEL
  4. COMPUTE NODES
  5. CACHING
  6. Caches
  7. Consistency and Coherence
  8. MEMORY NODES
  9. VIRTUAL MEMORY
  10. INTERCONNECTS AND NETWORKING
  11. STORAGE
  12. DESIGNING AND PROTOTYPING
  13. MANAGEMENT
  14. Resource Monitoring
  15. Software Defined Architecture
  16. ...and 1 more sections

Figures (3)

  • Figure 1: High-level system architectures for memory disaggregation
  • Figure 2: Extended memory hierarchy in the datacenter
  • Figure 3: An example of our proposed architecture. The upper layer represents heterogeneous compute nodes, with their local DRAMs functioning as caches. The middle layer represents one level of FPGA based caching. The bottom layer represents a hybrid remote memory/storage as well as NICs interfacing with the outside world. The interconnect is simplified and does not show the topology nor the switching infrastructure also serving as directories.