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SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans

Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini

TL;DR

SCARF addresses fabrication-time Hardware Trojans in fabless ICs by unifying front-end repurposing of verification assertions with back-end online monitors inserted during physical synthesis. It introduces Security Coverage (SC) to quantify HT-detection effectiveness and demonstrates automated assertion selection, synthesis-to-TAINT analysis, and ECO-based monitor insertion. Experimental results across OpenTitan IPs show SC gains up to 33.5% with area/power increments typically below 20%, and additional SC improvements from online monitors up to 33.5% depending on design. The work offers a holistic defense spanning design stages, improving robustness against HTs while maintaining practical PPA budgets, and outlines a path for further optimization and path-aware enhancements.

Abstract

The globalization of the semiconductor industry has introduced security challenges to Integrated Circuits (ICs), particularly those related to the threat of Hardware Trojans (HTs) - malicious logic that can be introduced during IC fabrication. While significant efforts are directed towards verifying the correctness and reliability of ICs, their security is often overlooked. In this paper, we propose a comprehensive approach to enhance IC security from the front-end to back-end stages of design. Initially, we outline a systematic method to transform existing verification assets into potent security checkers by repurposing verification assertions. To further improve security, we introduce an innovative technique for integrating online monitors during physical synthesis - a back-end insertion providing an additional layer of defense. Experimental results demonstrate a significant increase in security, measured by our introduced metric, Security Coverage (SC), with a marginal rise in area and power consumption, typically under 20%. The insertion of online monitors during physical synthesis enhances security metrics by up to 33.5%. This holistic approach offers a comprehensive and resilient defense mechanism across the entire spectrum of IC design.

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans

TL;DR

SCARF addresses fabrication-time Hardware Trojans in fabless ICs by unifying front-end repurposing of verification assertions with back-end online monitors inserted during physical synthesis. It introduces Security Coverage (SC) to quantify HT-detection effectiveness and demonstrates automated assertion selection, synthesis-to-TAINT analysis, and ECO-based monitor insertion. Experimental results across OpenTitan IPs show SC gains up to 33.5% with area/power increments typically below 20%, and additional SC improvements from online monitors up to 33.5% depending on design. The work offers a holistic defense spanning design stages, improving robustness against HTs while maintaining practical PPA budgets, and outlines a path for further optimization and path-aware enhancements.

Abstract

The globalization of the semiconductor industry has introduced security challenges to Integrated Circuits (ICs), particularly those related to the threat of Hardware Trojans (HTs) - malicious logic that can be introduced during IC fabrication. While significant efforts are directed towards verifying the correctness and reliability of ICs, their security is often overlooked. In this paper, we propose a comprehensive approach to enhance IC security from the front-end to back-end stages of design. Initially, we outline a systematic method to transform existing verification assets into potent security checkers by repurposing verification assertions. To further improve security, we introduce an innovative technique for integrating online monitors during physical synthesis - a back-end insertion providing an additional layer of defense. Experimental results demonstrate a significant increase in security, measured by our introduced metric, Security Coverage (SC), with a marginal rise in area and power consumption, typically under 20%. The insertion of online monitors during physical synthesis enhances security metrics by up to 33.5%. This holistic approach offers a comprehensive and resilient defense mechanism across the entire spectrum of IC design.
Paper Structure (26 sections, 2 equations, 12 figures, 3 tables)

This paper contains 26 sections, 2 equations, 12 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Detection Techniques
  4. DfHT Techniques
  5. Threat Model
  6. Related Works
  7. Logic Locking
  8. Layout Filling
  9. Online Monitors
  10. Reusing Verification Assertions as HT detector
  11. Security Coverage
  12. Evaluation of the Security Properties of Verification Assertions
  13. Challenges
  14. Enhancing the Security by Adding Online Monitors during the Physical Synthesis
  15. Online Monitors
  16. ...and 11 more sections

Figures (12)

  • Figure 1: An overview of the HT protection methods. The techniques used in this work are colored in green.
  • Figure 2: Different stages of IC design: The design house and the test house are considered trusted, while the foundry is assumed to be untrusted.
  • Figure 3: An example of a) original design, b) nodes covered by bound assertion Assr_1, and c) nodes covered by bound assertion Assr_2
  • Figure 4: Optimization flow for selecting the assertions to be used as security checkers
  • Figure 5: SC percentage for different IPs of OpenTitan
  • ...and 7 more figures