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Evaluating Versal AI Engines for option price discovery in market risk analysis

Mark Klaisoongnoen, Nick Brown, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus

TL;DR

This paper evaluates whether Versal ACAP's AI Engines can accelerate a standard market-risk benchmark (SIMR/STAC-A2) by porting the VariancePathQE kernel to AIEs and coupling it with Programmable Logic. Across single- and multi-AIE configurations, and in comparison with a PL-only implementation on Versal and on an Alveo U280, the study finds that AIE-based designs underperform the optimized PL solution due to architectural and tooling constraints, including dataflow inefficiencies, loopback overhead, and AXI-interface bottlenecks. The work provides detailed insights into dataflow design, AIE vectorization, and PL-AIE integration challenges, offering practical guidance for designing FPGA-based financial analytics accelerators. The findings underscore the current limitations of AIE-centric approaches for tightly coupled, cycle-accurate financial workloads and emphasize optimizing PL pathways for performance-critical market risk analysis. These insights are broadly applicable to high-performance numerical modelling on next-generation FPGA platforms.

Abstract

Whilst Field-Programmable Gate Arrays (FPGAs) have been popular in accelerating high-frequency financial workload for many years, their application in quantitative finance, the utilisation of mathematical models to analyse financial markets and securities, is less mature. Nevertheless, recent work has demonstrated the benefits that FPGAs can deliver to quantitative workloads, and in this paper, we study whether the Versal ACAP and its AI Engines (AIEs) can also deliver improved performance. We focus specifically on the industry standard Strategic Technology Analysis Center's (STAC) derivatives risk analysis benchmark STAC-A2. Porting a purely FPGA-based accelerator STAC-A2 inspired market risk (SIMR) benchmark to the Versal ACAP device by combining Programmable Logic (PL) and AIEs, we explore the development approach and techniques, before comparing performance across PL and AIEs. Ultimately, we found that our AIE approach is slower than a highly optimised existing PL-only version due to limits on both the AIE and PL that we explore and describe.

Evaluating Versal AI Engines for option price discovery in market risk analysis

TL;DR

This paper evaluates whether Versal ACAP's AI Engines can accelerate a standard market-risk benchmark (SIMR/STAC-A2) by porting the VariancePathQE kernel to AIEs and coupling it with Programmable Logic. Across single- and multi-AIE configurations, and in comparison with a PL-only implementation on Versal and on an Alveo U280, the study finds that AIE-based designs underperform the optimized PL solution due to architectural and tooling constraints, including dataflow inefficiencies, loopback overhead, and AXI-interface bottlenecks. The work provides detailed insights into dataflow design, AIE vectorization, and PL-AIE integration challenges, offering practical guidance for designing FPGA-based financial analytics accelerators. The findings underscore the current limitations of AIE-centric approaches for tightly coupled, cycle-accurate financial workloads and emphasize optimizing PL pathways for performance-critical market risk analysis. These insights are broadly applicable to high-performance numerical modelling on next-generation FPGA platforms.

Abstract

Whilst Field-Programmable Gate Arrays (FPGAs) have been popular in accelerating high-frequency financial workload for many years, their application in quantitative finance, the utilisation of mathematical models to analyse financial markets and securities, is less mature. Nevertheless, recent work has demonstrated the benefits that FPGAs can deliver to quantitative workloads, and in this paper, we study whether the Versal ACAP and its AI Engines (AIEs) can also deliver improved performance. We focus specifically on the industry standard Strategic Technology Analysis Center's (STAC) derivatives risk analysis benchmark STAC-A2. Porting a purely FPGA-based accelerator STAC-A2 inspired market risk (SIMR) benchmark to the Versal ACAP device by combining Programmable Logic (PL) and AIEs, we explore the development approach and techniques, before comparing performance across PL and AIEs. Ultimately, we found that our AIE approach is slower than a highly optimised existing PL-only version due to limits on both the AIE and PL that we explore and describe.
Paper Structure (11 sections, 3 figures, 3 tables)

This paper contains 11 sections, 3 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Previous acceleration of the SIMR benchmark on programmable logic (PL)
  4. The Versal Adaptive Compute Acceleration Platform (ACAP) and AI engine (AIE)
  5. Experimental setup
  6. Single AIE graph development
  7. Coupling AI Engines with the PL
  8. Programmable logic (PL) code
  9. Single AIE graph performance
  10. Multi AIE graph performance
  11. Conclusions

Figures (3)

  • Figure 1: Illustration of the dataflow design where stages are running concurrently connected via HLS streams stac-a2-h2rc
  • Figure 2: Graph for multi-AIE with ten kernels as presented in Table \ref{['tab:single_aie_kernel_cycles']}.
  • Figure 3: Illustration of the loopback adaptor on the PL used to support the cycling of data between AIE iterations