Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells

TL;DR

It is concluded that, beyond static variability, the dynamic noise inflates defectiveness among SRAM bitcells and the limits of existing analytical formulas are discussed, which rely on a linear near-equilibrium approximation of the SRAM dynamics to predict the mean time to failure.

Abstract

Stability of ultra-low-voltage SRAM bitcells in retention mode is threatened by two types of uncertainty: process variability and intrinsic noise. While variability dominates the failure probability, noise-induced bit flips in weakened bitcells lead to dynamic instability. We study both effects jointly in a unified SPICE simulation framework. Starting from a synthetic representation of process variations introduced in a previous work, we identify the cases of poor noise immunity that require thorough noise analyses. Relying on a rigorous and systematic methodology, we simulate them in the time domain so as to emulate a true data retention operation. Short times to failure, unacceptable for a practical ultra-low-power memory system application, are recorded. The transient bit-flip mechanism is analysed and a dynamic failure criterion involving the unstable point is established. We conclude that, beyond static variability, the dynamic noise inflates defectiveness among SRAM bitcells. We also discuss the limits of existing analytical formulas from the literature, which rely on a linear near-equilibrium approximation of the SRAM dynamics to, inaccurately, predict the mean time to failure.

Figures (4)

• Figure 1: 6T SRAM bitcell. Data retention is ensured by the cross-coupled inverter pair ($M_1$ and $M_2$, $M_3$ and $M_4$), like in 8T and 10T architectures.
• Figure 2: \ref{['fig_2D']} 2D representation of functional and defective SRAM bitcells in presence of process variability, deterministically simulated with a double DC sweep of variations $(\delta V_1,\delta V_2)$ applied at the inputs of the inverters ($M_1$ and $M_2$, $M_3$ and $M_4$ in \ref{['fig_6T_SRAM']}). The orange crown contains the bitcells of positive but low $SNM$ ($\leq 10mV$). Voltage step of the double DC sweep : $\Delta \delta V = 1mV$. \ref{['fig_butterfly']} Butterfly plots of three special cases marked by dots in \ref{['fig_2D']}, along the line $\delta V_1 = -\delta V_2$ corresponding to the worse-case scenario where both inverters are adversely affected. For functional bitcells, the $SNM$ is the width of the largest inscribed square. Illustrated case: $28nm$ FD-SOI Single-P-Well (SPW) SRAM cell (inverters made of RVT nMOS and LVT pMOS; RVT nMOS access transistors $M_5$ and $M_6$) of minimal transistor dimensions $L_\mathrm{n} = L_\mathrm{p} = 30nm$ and $W_\mathrm{n} = W_\mathrm{p} = 80nm$, $V_{\mathrm{PW}} \equiv V_{\mathrm{B}} = 0$, operating at $V_{\mathrm{DD}} = 200mV$ and room temperature ($T = 300K$).
• Figure 3: \ref{['fig_bit_flip']} Transient simulation of a noise-induced hold failure of a 6T SRAM bitcell (\ref{['fig_6T_SRAM']}). \ref{['fig_state_space']} State trajectory of the bit flip of \ref{['fig_bit_flip']} in the state space. Illustrated case: same SRAM design as \ref{['fig_2D_butterfly']}, with process variations $\delta V_1 = -\delta V_2 = 58mV$. Bandwidth of the generated noise: $f_{\mathrm{max}} = 1GHz$ ($\mathop{}\!\mathrm{d}{t} = 500ps$).
• Figure 4: $MTTF$empirically estimated from transient noise simulations (averaged over 100.0 experiments like \ref{['fig_bit_flip']}, for each point) compared to the predictions of the analytical formulas.