Designing Silicon Brains using LLM: Leveraging ChatGPT for Automated Description of a Spiking Neuron Array

TL;DR

The paper addresses translating natural-language prompts into a synthesizable Verilog description of a programmable spiking neuron array using ChatGPT-4, enabling an end-to-end hardware design flow that includes a leaky integrate-and-fire neuron, a two-layer network with programmable synapses, an SPI interface, and a top-level controller. It validates the approach through handcrafted testbenches and a Tiny Tapeout submission on Skywater 130nm, highlighting iterative debugging and prompts required to fix syntax, logic, and Verilog-style issues. The key contributions are the documented NL-to-HDL workflow, a complete HDL including SPI and network modules, and a realistic assessment of the current limitations of LLM-assisted hardware design, including the need for domain expertise to ensure correctness and verifiability. Overall, the work demonstrates potential for accelerating foundational HDL generation from natural language while underscoring the reliability gaps and verification burden present today.

Abstract

Large language models (LLMs) have made headlines for synthesizing correct-sounding responses to a variety of prompts, including code generation. In this paper, we present the prompts used to guide ChatGPT4 to produce a synthesizable and functional verilog description for the entirety of a programmable Spiking Neuron Array ASIC. This design flow showcases the current state of using ChatGPT4 for natural language driven hardware design. The AI-generated design was verified in simulation using handcrafted testbenches and has been submitted for fabrication in Skywater 130nm through Tiny Tapeout 5 using an open-source EDA flow.

Figures (1)

• Figure 1: Two layer fully connected neuron network.