A Novel Computing Paradigm for MobileNetV3 using Memristor

TL;DR

The paper tackles the challenge of deploying deep neural networks on resource-constrained edge devices by introducing a memristor-based computing paradigm for MobileNetV3. It details four memristor-enabled neural units (convolution, batch normalization, activation, pooling, and fully connected) and an automated framework that maps trained weights to memristor conductances and generates SPICE netlists for validation. On CIFAR-10, the approach achieves over 90% accuracy while delivering dramatic gains in speed and energy efficiency, including a reported speedup of around 138x over GPUs and 2827x over CPUs, and energy savings of up to 61.7x versus CPU. The combination of hardware-aware module designs and a high-level synthesis framework enables rapid exploration of memristor-based DNNs, paving the way for practical, low-power edge AI deployments.

Abstract

The increasing computational demands of deep learning models pose significant challenges for edge devices. To address this, we propose a memristor-based circuit design for MobileNetV3, specifically for image classification tasks. Our design leverages the low power consumption and high integration density of memristors, making it suitable for edge computing. The architecture includes optimized memristive convolutional modules, batch normalization modules, activation function modules, global average pooling modules, and fully connected modules. Experimental results on the CIFAR-10 dataset show that our memristor-based MobileNetV3 achieves over 90% accuracy while significantly reducing inference time and energy consumption compared to traditional implementations. This work demonstrates the potential of memristor-based designs for efficient deployment of deep learning models in resource-constrained environments.

Figures (8)

• Figure 1: Flowchart of the network architecture based on MobileNetV3.
• Figure 2: Circuit schematic of memristor crossbars for a convolution operation.
• Figure 3: Circuit schematic of memristor crossbars for a batch normalization operation. (a) $\gamma\geq0$, $\beta>0$ (b) $\gamma<0$, $\beta<0$.
• Figure 4: Circuit schematic of an activation function operation. (a) hard sigmoid, (b) hard swish, and simulation result (c) hard sigmoid, (d) hard swish.
• Figure 5: Circuit schematic of memristor crossbars for (a) a global average pooling operation, (b) a fully connected operation.