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The Vienna Architecture Description Language

Florian Freitag, Linus Halder, Simon Himmelbauer, Christoph Hochrainer, Benedikt Huber, Benjamin Kasper, Niklas Mischkulnig, Michael Nestler, Philipp Paulweber, Kevin Per, Matthias Raschhofer, Alexander Ripar, Tobias Schwarzinger, Johannes Zottele, Andreas Krall

TL;DR

VADL introduces a high-level, generator-oriented language that cleanly separates ISA semantics from microarchitecture, enabling automatic generation of toolchains and hardware artifacts from a single specification. The architecture combines a typed macro-rich ISA description with a higher-level MiA model and leverages multiple IRs (VIR/VIAM) and generators (compiler, assembler, QEMU ISS, CAS, HDL) to produce LLVM backends, simulators, and synthesizable hardware. The paper provides extensive evaluation across ISA and MiA expressiveness, showcases OpenVADL improvements over the original, and discusses limitations and future work in areas like memory models, verification, and JIT backends. Overall, VADL enables rapid design space exploration of ASIPs by reducing manual backends engineering and enabling cohesive generation of software and hardware artifacts.

Abstract

The Vienna Architecture Description Language (VADL) is a powerful processor description language (PDL) that enables the concise formal specification of processor architectures. By utilizing a single VADL processor specification, the VADL system exhibits the capability to automatically generate a range of artifacts necessary for rapid design space exploration. These include assemblers, compilers, linkers, functional instruction set simulators, cycle-accurate instruction set simulators, synthesizable specifications in a hardware description language, as well as test cases and documentation. One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge. The original VADL implementation has a restricted copyright. Therefore, the open source implementation OpenVADL was started. This article introduces VADL, compares the original VADL implementation with the ongoing OpenVADL implementation, describes the generator techniques in detail and demonstrates the power of the language and the performance of the generators in an empirical evaluation. The evaluation shows the expressiveness and conciseness of VADL and the efficiency of the generated artifacts.

The Vienna Architecture Description Language

TL;DR

VADL introduces a high-level, generator-oriented language that cleanly separates ISA semantics from microarchitecture, enabling automatic generation of toolchains and hardware artifacts from a single specification. The architecture combines a typed macro-rich ISA description with a higher-level MiA model and leverages multiple IRs (VIR/VIAM) and generators (compiler, assembler, QEMU ISS, CAS, HDL) to produce LLVM backends, simulators, and synthesizable hardware. The paper provides extensive evaluation across ISA and MiA expressiveness, showcases OpenVADL improvements over the original, and discusses limitations and future work in areas like memory models, verification, and JIT backends. Overall, VADL enables rapid design space exploration of ASIPs by reducing manual backends engineering and enabling cohesive generation of software and hardware artifacts.

Abstract

The Vienna Architecture Description Language (VADL) is a powerful processor description language (PDL) that enables the concise formal specification of processor architectures. By utilizing a single VADL processor specification, the VADL system exhibits the capability to automatically generate a range of artifacts necessary for rapid design space exploration. These include assemblers, compilers, linkers, functional instruction set simulators, cycle-accurate instruction set simulators, synthesizable specifications in a hardware description language, as well as test cases and documentation. One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge. The original VADL implementation has a restricted copyright. Therefore, the open source implementation OpenVADL was started. This article introduces VADL, compares the original VADL implementation with the ongoing OpenVADL implementation, describes the generator techniques in detail and demonstrates the power of the language and the performance of the generators in an empirical evaluation. The evaluation shows the expressiveness and conciseness of VADL and the efficiency of the generated artifacts.
Paper Structure (77 sections, 20 figures, 6 tables, 1 algorithm)

This paper contains 77 sections, 20 figures, 6 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Contribution
  3. Outline
  4. Background
  5. The Processor Description Language
  6. Introduction
  7. Strict Separation of ISA and MiA
  8. Language Safety
  9. Overview
  10. Instruction Set Architecture Section
  11. Micro Architecture Section
  12. Pipeline Stage
  13. Instruction Abstraction
  14. An Exemplary Pipeline
  15. Logic Elements
  16. ...and 62 more sections

Figures (20)

  • Figure 1: Overview of the original VADL and OpenVADL Compiler Architecture. Yellow boxes represent generators.
  • Figure 2: VIAM behavior graph of the RISC-V ADD instruction
  • Figure 3: Compiler Generator Overview
  • Figure 4: ADD instruction's semantics
  • Figure 5: Overview of Generated Components and Their Inputs and Outputs. Red Boxes Denote External Representations.
  • ...and 15 more figures