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CycPUF: Cyclic Physical Unclonable Function

Michael Dominguez, Amin Rezaei

TL;DR

This paper introduces CycPUF, a framework that injects feedback into delay-based PUFs to create cyclic variants of APUF, ROPUF, and BPUF, thereby expanding output behaviors into multiple response modes under fixed challenges. By employing Challenge-Response Modes (CRMs) that yield multiple CRP-equivalents, CycPUF makes modeling attacks harder while maintaining favorable PUF metrics. FPGA-based implementations demonstrate substantially improved resistance to ML-based and fault-injection modeling attacks, with CycPUFs achieving near-ideal uniqueness and competitive reliability and uniformity, albeit with moderate hardware and power overheads. The work highlights cyclic combinational circuits as a promising direction for secure, synthesis-friendly hardware security primitives and suggests avenues for broader adoption and tooling development.

Abstract

Physical Unclonable Functions (PUFs) leverage manufacturing process imperfections that cause propagation delay discrepancies for the signals traveling along these paths. While PUFs can be used for device authentication and chip-specific key generation, strong PUFs have been shown to be vulnerable to machine learning modeling attacks. Although there is an impression that combinational circuits must be designed without any loops, cyclic combinational circuits have been shown to increase design security against hardware intellectual property theft. In this paper, we introduce feedback signals into traditional delay-based PUF designs such as arbiter PUF, ring oscillator PUF, and butterfly PUF to give them a wider range of possible output behaviors and thus an edge against modeling attacks. Based on our analysis, cyclic PUFs produce responses that can be binary, steady-state, oscillating, or pseudo-random under fixed challenges. The proposed cyclic PUFs are implemented in field programmable gate arrays, and their power and area overhead, in addition to functional metrics, are reported compared with their traditional counterparts. The security gain of the proposed cyclic PUFs is also shown against state-of-the-art attacks.

CycPUF: Cyclic Physical Unclonable Function

TL;DR

This paper introduces CycPUF, a framework that injects feedback into delay-based PUFs to create cyclic variants of APUF, ROPUF, and BPUF, thereby expanding output behaviors into multiple response modes under fixed challenges. By employing Challenge-Response Modes (CRMs) that yield multiple CRP-equivalents, CycPUF makes modeling attacks harder while maintaining favorable PUF metrics. FPGA-based implementations demonstrate substantially improved resistance to ML-based and fault-injection modeling attacks, with CycPUFs achieving near-ideal uniqueness and competitive reliability and uniformity, albeit with moderate hardware and power overheads. The work highlights cyclic combinational circuits as a promising direction for secure, synthesis-friendly hardware security primitives and suggests avenues for broader adoption and tooling development.

Abstract

Physical Unclonable Functions (PUFs) leverage manufacturing process imperfections that cause propagation delay discrepancies for the signals traveling along these paths. While PUFs can be used for device authentication and chip-specific key generation, strong PUFs have been shown to be vulnerable to machine learning modeling attacks. Although there is an impression that combinational circuits must be designed without any loops, cyclic combinational circuits have been shown to increase design security against hardware intellectual property theft. In this paper, we introduce feedback signals into traditional delay-based PUF designs such as arbiter PUF, ring oscillator PUF, and butterfly PUF to give them a wider range of possible output behaviors and thus an edge against modeling attacks. Based on our analysis, cyclic PUFs produce responses that can be binary, steady-state, oscillating, or pseudo-random under fixed challenges. The proposed cyclic PUFs are implemented in field programmable gate arrays, and their power and area overhead, in addition to functional metrics, are reported compared with their traditional counterparts. The security gain of the proposed cyclic PUFs is also shown against state-of-the-art attacks.
Paper Structure (13 sections, 6 equations, 6 figures, 2 tables)

This paper contains 13 sections, 6 equations, 6 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Threat Model
  4. Preliminaries
  5. Uniqueness
  6. Reliability
  7. Uniformity
  8. Cyclic PUF
  9. Experimental Results
  10. Security Evaluation
  11. Overhead Measurement
  12. Functional Metrics Analysis
  13. Conclusion

Figures (6)

  • Figure 1: CycPUF framework
  • Figure 2: CycPUF binary response mode
  • Figure 3: CycPUF steady-state response mode
  • Figure 4: CycPUF oscillating response mode
  • Figure 5: CycPUF pseudo-random response mode
  • ...and 1 more figures