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IR-Aware ECO Timing Optimization Using Reinforcement Learning

Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar

TL;DR

This work addresses IR-induced timing failures in late-stage IC design by coupling IR-aware timing analysis with ECO gate sizing through a reinforcement learning framework guided by Lagrangian relaxation. A relational graph convolutional network (R-GCN) agent sequentially upsizes or downsizes gates on a problem-constrained, post-P&R netlist, using a state that encompasses negative slack regions and an action mask that limits changes to critical-area cells. The LR-based reward and LM updates enable efficient constrained optimization, while problem-specific strategies (action-space reduction, clock-schedule, and LM adaptation) enhance training efficiency and transferability. Evaluation on 45nm benchmarks shows the approach shifts the power-delay Pareto frontier left, reduces runtime, and achieves consistent timing recovery with smaller placement perturbations, with zero-shot and fine-tuning transferability across designs. Overall, the method offers a practical, transferable framework for IR-aware ECO timing that blends traditional LR insights with modern graph-based RL for constrained, low-perturbation optimization.

Abstract

Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis and ECO timing optimization using reinforcement learning (RL). The method operates after physical design and power grid synthesis, and rectifies IR-drop-induced timing degradation through gate sizing. It incorporates the Lagrangian relaxation (LR) technique into a novel RL framework, which trains a relational graph convolutional network (R-GCN) agent to sequentially size gates to fix timing violations. The R-GCN agent outperforms a classical LR-only algorithm: in an open 45nm technology, it (a) moves the Pareto front of the delay-power tradeoff curve to the left (b) saves runtime over the prior approaches by running fast inference using trained models, and (c) reduces the perturbation to placement by sizing fewer cells. The RL model is transferable across timing specifications and to unseen designs with fine tuning.

IR-Aware ECO Timing Optimization Using Reinforcement Learning

TL;DR

This work addresses IR-induced timing failures in late-stage IC design by coupling IR-aware timing analysis with ECO gate sizing through a reinforcement learning framework guided by Lagrangian relaxation. A relational graph convolutional network (R-GCN) agent sequentially upsizes or downsizes gates on a problem-constrained, post-P&R netlist, using a state that encompasses negative slack regions and an action mask that limits changes to critical-area cells. The LR-based reward and LM updates enable efficient constrained optimization, while problem-specific strategies (action-space reduction, clock-schedule, and LM adaptation) enhance training efficiency and transferability. Evaluation on 45nm benchmarks shows the approach shifts the power-delay Pareto frontier left, reduces runtime, and achieves consistent timing recovery with smaller placement perturbations, with zero-shot and fine-tuning transferability across designs. Overall, the method offers a practical, transferable framework for IR-aware ECO timing that blends traditional LR insights with modern graph-based RL for constrained, low-perturbation optimization.

Abstract

Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis and ECO timing optimization using reinforcement learning (RL). The method operates after physical design and power grid synthesis, and rectifies IR-drop-induced timing degradation through gate sizing. It incorporates the Lagrangian relaxation (LR) technique into a novel RL framework, which trains a relational graph convolutional network (R-GCN) agent to sequentially size gates to fix timing violations. The R-GCN agent outperforms a classical LR-only algorithm: in an open 45nm technology, it (a) moves the Pareto front of the delay-power tradeoff curve to the left (b) saves runtime over the prior approaches by running fast inference using trained models, and (c) reduces the perturbation to placement by sizing fewer cells. The RL model is transferable across timing specifications and to unseen designs with fine tuning.
Paper Structure (15 sections, 8 equations, 7 figures, 5 tables)

This paper contains 15 sections, 8 equations, 7 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Problem formulation
  3. RL-LR ECO timing framework
  4. The circuit netlist as an annotated graph
  5. Mapping IR-aware gate sizing to RL
  6. Application of the R-GCN agent
  7. RL model training
  8. Core training strategy
  9. Problem-specific training enhancement
  10. Evaluation of RL-LR ECO
  11. Experimental setup
  12. Optimization and delay-power tradeoffs
  13. Importance of LR-based weight adaptation
  14. Transferability across designs
  15. Conclusion

Figures (7)

  • Figure 1: State and action spaces from the circuit netlist.
  • Figure 2: R-GCN aggregation from a 3-hop neighborhood.
  • Figure 3: Structure of the three-layered R-GCN agent.
  • Figure 4: Overview of the RL-based ECO gate sizing flow.
  • Figure 5: Results of training, showing the convergence of the WNS and TNS.
  • ...and 2 more figures