A programmable photonic memory

TL;DR

The paper tackles the challenge of optical memory by proposing a scalable, integrated memory unit built from universal optical logic gates implemented with nonlinear micro-ring modulators on a silicon photonic platform. The approach yields an optical set-reset latch with optical set, reset, and outputs $Q$ and $\overline{Q}$, realized via cross-coupled NOR/NAND gates and an independent supply-light inverter at $\lambda_{0}$. Experimental verification of NOR/NAND gates on a programmable silicon-photonic mesh, along with simulator-assisted SR-latch validation on a larger mesh, demonstrates correct logic operation and latch behavior with robustness to input variations. This work paves the way for co-integrated, low-latency optical memories compatible with existing photonic processors, enabling scalable and energy-efficient optical computation pipelines.

Abstract

The significant advancements in integrated photonics have enabled high-speed and energy efficient systems for various applications from data communications and high-performance computing, to medical diagnosis, sensing and ranging. However, data storage in these systems has been dominated by electronic memories which necessitates signal conversion between optical and electrical as well as analog and digital domains, and data movement between processor and memory that reduce the speed and energy efficiency. To date, a scalable optical memory with optical control has remained an open problem. Here we report an integrated photonic set-reset latch as a fundamental optical static memory unit based on universal optical logic gates. While the proposed memory is compatible with different photonic platforms, its functionality is demonstrated on a programmable silicon photonic chip as a proof of concept. Optical set, reset, and complementary outputs, scalability to a large number of memory units via the independent latch supply light, and compatibility with different photonic platforms enable more efficient and lower latency optical processing systems.

Figures (6)

• Figure 1: Comparing electronic and optical memory interfaces in an optical processor.a An optical processor with electronic memory. Optical data to be stored in the memory should be photo-detected, digitized, and transferred to the electronic memory. Similarly, to retrieve data, it should be transferred and converted to analog signals that modulate an optical carrier to up-convert the data to optical domain to be processed by the system. b Optical processor with embedded optical memory. E-O and O-E conversions, ADC and DAC, and electronic data movement can be eliminated, resulting in lower latency, higher energy efficiency, smaller the system size, and less packaging complexities.
• Figure 2: Universal optical logic gates.a Photonic NOR circuit consisting of two MRMs to generate the maximum of the two inputs (OR operation) followed by MRM C to perform NOT operation and b Transmission spectra for different logic input combinations. c Photonic NAND circuit consisting of two MRMs to generate the minimum of the two inputs (AND operation) followed by MRM C to perform NOT operation and d Transmission spectra for different logic input combinations. e Schematic of an optical SR latch and the corresponding truth tables using (i) two NOR and (ii) two NAND gates. f Photonic SR latch circuit using two cross-coupled NOR gates.
• Figure 3: Implementation of NOR/NAND gates on the hardware mesh.a Schematic of the hardware mesh made with 2$\times$2 MZIs. The signal path for signals A, B, and supply light are marked with black, grey, and red lines, respectively. Green lines mark the paths with multiple signals. b Experimental results for NOR and NAND gates. Arbitrary amplitude variations are added to the input signals to ensure robustness. In each graph, vertical axis shows the normalized amplitude and horizontal axis shows the input sequence.
• Figure 4: Optical SR latch on programmable MZI mesh.a Schematic of the simulator mesh made with 2$\times$2 MZIs. The mesh size allows for having two coupled UOLGs. For each gate, the signal path for signals A, B, and supply light are marked with black, grey, and red lines. Set and reset attenuators are shown in blue and red, respectively. Green lines mark the paths with multiple signals. b Simulation results of the SR latch circuit. Different combinations of set (blue) and reset (red) signals are generated and the corresponding complimentary outputs $Q$ and $\overline{Q}$ are plotted.
• Figure S1: Schematic of the NOR/NAND circuit implemented on the hardware mesh shown in Fig. 3a of the main text.