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BetterV: Controlled Verilog Generation with Discriminative Guidance

Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu

TL;DR

This work tackles the challenge of automated Verilog generation under strict correctness and downstream-EDA constraints. It introduces BetterV, which combines domain-specific instruct-tuning of LLMs with task-focused generative discriminators and data augmentation to guide Verilog output for downstream goals like synthesis and SAT-based verification. The approach yields state-of-the-art VerilogEval performance and meaningful downstream gains, including substantial synthesis-node reductions and reduced verification runtimes, demonstrating practical impact for IC design. By grounding Verilog in learned C representations, augmenting data, and deploying task-aware discriminators, BetterV reduces design iterations and offers a scalable path to precision-driven HDL generation in EDA and potentially other domains with structured languages.

Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.

BetterV: Controlled Verilog Generation with Discriminative Guidance

TL;DR

This work tackles the challenge of automated Verilog generation under strict correctness and downstream-EDA constraints. It introduces BetterV, which combines domain-specific instruct-tuning of LLMs with task-focused generative discriminators and data augmentation to guide Verilog output for downstream goals like synthesis and SAT-based verification. The approach yields state-of-the-art VerilogEval performance and meaningful downstream gains, including substantial synthesis-node reductions and reduced verification runtimes, demonstrating practical impact for IC design. By grounding Verilog in learned C representations, augmenting data, and deploying task-aware discriminators, BetterV reduces design iterations and offers a scalable path to precision-driven HDL generation in EDA and potentially other domains with structured languages.

Abstract

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.
Paper Structure (22 sections, 10 equations, 4 figures, 5 tables)

This paper contains 22 sections, 10 equations, 4 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. LLMs for Verilog Generation
  4. Discriminator-guided Controllable Generation
  5. Algorithm
  6. Framework Overview
  7. Instruct-Tuning Data-Processing
  8. Domain-specific Instruct-Tuning
  9. Data Augmentation
  10. Generative Discriminator
  11. Experiments
  12. Experimental Setting
  13. Functional Correctness
  14. Customized Generation in BetterV
  15. Synthesis Nodes Reduction
  16. ...and 7 more sections

Figures (4)

  • Figure 1: The overview of BetterV.
  • Figure 2: The examples for instruct-tuning. We take a simple d_latch Verilog module as example. The left and right part indicate the code knowledge transfer and Verilog autocompletion, respectively.
  • Figure 3: An example shows the guidance from generative discriminator.
  • Figure 4: An example to instruct the LLMs to rewrite the Verilog module to reduce the AIG nodes after synthesis.