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Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, Jeyavijayan Rajendran

TL;DR

The paper tackles the problem of generating high-quality Verilog RTL code with explicit power, performance, and area ($PPA$) considerations, addressing compilation failures and functional gaps in existing LLM-based approaches. It introduces VeriGen+MCTS, an MCTS-guided decoding framework that combines token-level probabilities from a fine-tuned LLM with synthesis feedback to produce compilable and functionally correct RTL while optimizing the area-delay product ($ADP$). The approach uses two key innovations: pruning non-functional tokens to shrink the search space and modularity to reuse optimized submodules for large designs, enabling scalable synthesis of practical circuits. Experimental results show that VeriGen+MCTS consistently achieves functional correctness across 15 RTL problems and outperforms baseline greedy and beam-search methods, with average $ADP$ improvements of $5.69\%$ and $14.27\%$ respectively, and up to $31.8\%$ on a 16-bit adder. The work establishes a framework for reward-driven, searchable RTL code generation and highlights directions for scaling via fine-tuning and broader design coverage.

Abstract

Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

TL;DR

The paper tackles the problem of generating high-quality Verilog RTL code with explicit power, performance, and area () considerations, addressing compilation failures and functional gaps in existing LLM-based approaches. It introduces VeriGen+MCTS, an MCTS-guided decoding framework that combines token-level probabilities from a fine-tuned LLM with synthesis feedback to produce compilable and functionally correct RTL while optimizing the area-delay product (). The approach uses two key innovations: pruning non-functional tokens to shrink the search space and modularity to reuse optimized submodules for large designs, enabling scalable synthesis of practical circuits. Experimental results show that VeriGen+MCTS consistently achieves functional correctness across 15 RTL problems and outperforms baseline greedy and beam-search methods, with average improvements of and respectively, and up to on a 16-bit adder. The work establishes a framework for reward-driven, searchable RTL code generation and highlights directions for scaling via fine-tuning and broader design coverage.

Abstract

Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.
Paper Structure (15 sections, 2 equations, 4 figures, 3 tables)

This paper contains 15 sections, 2 equations, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background and related work
  3. Large Language Models for Code Generation
  4. LLMs for Verilog RTL Code Generation
  5. Framework
  6. Preliminary Formulation
  7. LLM-based Code Generation Using MCTS
  8. Reducing Search Space
  9. Improving Efficiency Through Modularity
  10. Putting It All Together
  11. Experimental Evaluation
  12. Experimental Setup
  13. LLM Efficacy Results
  14. Discussion and Future Work
  15. Conclusion

Figures (4)

  • Figure 2: Final MCTS framework
  • Figure 3: VeriGen+MCTS (a) initial and (b) final optimized functional codes for the 8-bit adder. Lines shaded gray highlight the differences. Note that baseline VeriGen does not produce a functionally correct code, so we do not have such a listing for it.
  • Figure 4: Impact of the baseline reward
  • Figure 5: Impact of the number of MCTS iterations