Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators

TL;DR

Problem: Selecting and configuring AI hardware accelerators for DNN workloads is challenging due to diverse architectures and opaque performance claims. Approach: ACADL provides an instruction-centric ADL with a formal timing semantics, implemented in C++ with a Python front-end, to model AI accelerators and map DNN operators via TVM and UMA. Contributions: three modeling examples (One MAC Accelerator, parameterizable systolic array, Goenna), plus detailed timing semantics and templates to generate architectures; demonstration of operator mapping and fast performance estimation. Significance: the framework supports hardware-aware NAS and DNN/HW co-design, enabling faster, more reliable design-space exploration.

Abstract

Artificial Intelligence (AI) has witnessed remarkable growth, particularly through the proliferation of Deep Neural Networks (DNNs). These powerful models drive technological advancements across various domains. However, to harness their potential in real-world applications, specialized hardware accelerators are essential. This demand has sparked a market for parameterizable AI hardware accelerators offered by different vendors. Manufacturers of AI-integrated products face a critical challenge: selecting an accelerator that aligns with their product's performance requirements. The decision involves choosing the right hardware and configuring a suitable set of parameters. However, comparing different accelerator design alternatives remains a complex task. Often, engineers rely on data sheets, spreadsheet calculations, or slow black-box simulators, which only offer a coarse understanding of the performance characteristics. The Abstract Computer Architecture Description Language (ACADL) is a concise formalization of computer architecture block diagrams, which helps to communicate computer architecture on different abstraction levels and allows for inferring performance characteristics. In this paper, we demonstrate how to use the ACADL to model AI hardware accelerators, use their ACADL description to map DNNs onto them, and explain the timing simulation semantics to gather performance results.

Figures (13)

• Figure 1: Class diagram of the Abstract Computer Architecture Description Language.
• Figure 2: Block diagram of the One MAC Accelerator (OMA).
• Figure 3: Architecture graph of the One MAC Accelerator (OMA).
• Figure 4: Block diagram of the systolic array architecture (excluding instruction memory and fetch unit).
• Figure 5: Architecture graph of the template for a PE of the parameterizable systolic array.