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Circuit Partitioning for Multi-Core Quantum Architectures with Deep Reinforcement Learning

Arnau Pastor, Pau Escofet, Sahar Ben Rached, Eduard Alarcón, Pere Barlet-Ros, Sergi Abadal

TL;DR

The paper tackles the scalability challenge of quantum computing by distributing qubits across multiple cores and framing circuit mapping as a graph-partitioning problem solvable by deep reinforcement learning. It introduces PPO-based and maskable PPO-based DRL models (Soft and Hard Mask variants) to minimize inter-core communications, using lookahead information and a timeslice-based framework. The Hard Mask variant achieves the strongest performance, surpassing the state-of-the-art FGP-rOEE on several benchmarks and generalizing across circuit families like Cuccaro and QAOA. The results suggest DRL is a viable direction for quantum circuit mapping with practical implications for multi-core quantum hardware design.

Abstract

Quantum computing holds immense potential for solving classically intractable problems by leveraging the unique properties of quantum mechanics. The scalability of quantum architectures remains a significant challenge. Multi-core quantum architectures are proposed to solve the scalability problem, arising a new set of challenges in hardware, communications and compilation, among others. One of these challenges is to adapt a quantum algorithm to fit within the different cores of the quantum computer. This paper presents a novel approach for circuit partitioning using Deep Reinforcement Learning, contributing to the advancement of both quantum computing and graph partitioning. This work is the first step in integrating Deep Reinforcement Learning techniques into Quantum Circuit Mapping, opening the door to a new paradigm of solutions to such problems.

Circuit Partitioning for Multi-Core Quantum Architectures with Deep Reinforcement Learning

TL;DR

The paper tackles the scalability challenge of quantum computing by distributing qubits across multiple cores and framing circuit mapping as a graph-partitioning problem solvable by deep reinforcement learning. It introduces PPO-based and maskable PPO-based DRL models (Soft and Hard Mask variants) to minimize inter-core communications, using lookahead information and a timeslice-based framework. The Hard Mask variant achieves the strongest performance, surpassing the state-of-the-art FGP-rOEE on several benchmarks and generalizing across circuit families like Cuccaro and QAOA. The results suggest DRL is a viable direction for quantum circuit mapping with practical implications for multi-core quantum hardware design.

Abstract

Quantum computing holds immense potential for solving classically intractable problems by leveraging the unique properties of quantum mechanics. The scalability of quantum architectures remains a significant challenge. Multi-core quantum architectures are proposed to solve the scalability problem, arising a new set of challenges in hardware, communications and compilation, among others. One of these challenges is to adapt a quantum algorithm to fit within the different cores of the quantum computer. This paper presents a novel approach for circuit partitioning using Deep Reinforcement Learning, contributing to the advancement of both quantum computing and graph partitioning. This work is the first step in integrating Deep Reinforcement Learning techniques into Quantum Circuit Mapping, opening the door to a new paradigm of solutions to such problems.
Paper Structure (13 sections, 3 figures)

This paper contains 13 sections, 3 figures.

Table of Contents

  1. Introduction
  2. Background
  3. Quantum Circuit Mapping for Multi-Core Architectures
  4. Deep Reinforcement Learning
  5. Proximal Policy Optimization
  6. MaskablePPO
  7. Deep Reinforcement Learning Exploration
  8. Approach 1: PPO
  9. Approach 2: Soft Mask
  10. Approach 3: Hard Mask
  11. DRL Models Discussion
  12. Performance Assessment
  13. Conclusions and Future Work

Figures (3)

  • Figure 1: Quantum circuit (timeslices in red) mapping into a modular architecture. The lower row shows how the mapping can be approached as a graph-partitioning problem.
  • Figure 2: Model performance within a 16 (upper row) and 32-qubit (lower row) modular quantum computer with four cores. Columns correspond to the evaluation metrics, from left to right, non-local communications, mean reward, and mean length.
  • Figure 3: Ratio between the state-of-the-art FGP-rOEE algorithm and the different maskable approaches