Neuromorphic Photonic Computing with an Electro-Optic Analog Memory

TL;DR

The paper tackles energy inefficiency in neuromorphic photonics caused by frequent data movement and DAC/ADC bottlenecks. It introduces Dynamic Electro-Optic Analog Memory (DEOAM), a monolithically integrated on-chip capacitive memory that co-locates with photonic compute units to significantly reduce DAC reliance and data movement. Through MNIST-based emulations and device-level measurements, it demonstrates substantial power savings (over 26x) and shows that maintaining a high memory retention-to-network-latency ratio preserves inference accuracy, while enabling leaky analog memories. The work also discusses scaling considerations, noise robustness, and future directions including new modulators and shared drive lines, outlining a practical path toward energy-efficient, high-speed neuromorphic photonic computing.

Abstract

In neuromorphic photonic systems, device operations are typically governed by analog signals, necessitating digital-to-analog converters (DAC) and analog-to-digital converters (ADC). However, data movement between memory and these converters in conventional von Neumann architectures incur significant energy costs. We propose an analog electronic memory co-located with photonic computing units to eliminate repeated long-distance data movement. Here, we demonstrate a monolithically integrated neuromorphic photonic circuit with on-chip capacitive analog memory and evaluate its performance in machine learning for in situ training and inference using the MNIST dataset. Our analysis shows that integrating analog memory into a neuromorphic photonic architecture can achieve over 26x power savings compared to conventional SRAM-DAC architectures. Furthermore, maintaining a minimum analog memory retention-to-network-latency ratio of 100 maintains >90% inference accuracy, enabling leaky analog memories without substantial performance degradation. This approach reduces reliance on DACs, minimizes data movement, and offers a scalable pathway toward energy-efficient, high-speed neuromorphic photonic computing.

Figures (5)

• Figure 1: Motivation for electro-optic processors with dynamic electro-optic analog memory (DEOAM). a) Dynamic electro-optic analog memory (DEOAM) consists of a capacitor connected to a PN junction microring resonator (MRR). The capacitor holds data on the MRR, thereby enacting a weight in the optical domain. Using DEOAM means DACs can be shared amongst columns of analog memory devices, updating them row by row since the analog memory holds the signal on the MRR, which relaxes limitations on energy efficiency and bandwidth imposed by DACs. b) Conventional electro-optic processors require a dedicated SRAM-DAC for each PN junction MRR. The DAC needs to be constantly active to hold a signal on the MRR; therefore, implementing SRAM-DAC in a neuromorphic photonic processor requires a DAC for every MRR. c) If $n$ represents the number of MRRs in the row and column of a neuromorphic photonic processor, scaling the conventional SRAM-DAC implementation incurs an $n\textsuperscript{2}$ DAC penalty, whereas DEOAM scales by $n$. Write power and sampling rate for 32x32, 8-bit memory cell architectures are compared using each memory device and DACs from literature ma_12-bit_2015ansari_5mw_2014kumar_impact_2021wu_130_2008hong_28nm_2015widmann_time-interleaved_2023zhang_06-v_2018kumar_performance_2017rubino_880_2023. As DEOAM scales, DEOAM saves more power compared to SRAM-DAC.
• Figure 2: The architecture and operation of the neuromorphic photonic prototype with integrated DEOAM. a) The analog memory circuit consists of a 1x4 MRR weight bank with each MRR connected to a capacitive analog memory. Transmission gates are used to enable/disable (EN) writing and switches are used to reset (RST) the analog memories. Laser light is injected into grating couplers through the IN port and is measured at the THRU and DROP ports. b) The operation of the DEOAM circuit is shown. The PN junction MRR is modeled as a reversed biased diode, and the transmission gate is modeled as an ideal switch. At time 1, the laser has been tuned to the MRR's resonance, and the transmission gate is connected such that the voltage source (VIN) can drive the analog memory (VPN). At time 2, voltage is driven onto the capacitor and MRR, causing the MRR's resonance to shift. At time 3, the transmission gate disconnects the voltage source from the capacitor, and the capacitor holds the charge on the MRR until it leaks away, returning the MRR resonance back to its original state. c) The chip is wire bonded to a custom printed circuit board with thermal control and high speed electrical lines. Details about the hardware operation and measurement setup are expanded in Methods.
• Figure 3: Electro-optic characteristics of the DEOAM. a) Leakage shows a dependence on optical power incident on the doped MRR. Error bands represent the standard deviation in the leakage. b) Retention time from leakage is 0.835 ms for one time constant ($\tau_{ret}$) at 0.5 dBm optical bus power. The decay shows a nonlinear response from the ring's Lorentzian response. c) With the transmission gate on, 2 V is written to analog memory using a 5 ns edge rate, and the resulting write time is 45.0 ns for one time constant ($\tau_{rise}$). d) With a source voltage of 2 V on $V\textsubscript{IN}$ and toggling the transmission gate from off to on, write time is 40.0 ns ($\tau_{rise}$). e) With the transmission gate on and writing 0 V to analog memory at an edge rate of 5 ns, write time is 51.0 ns for one time constant ($\tau_{fall}$). Further discussions on the electro-optic results are expanded in Supplementary Information.
• Figure 4: The neural network emulation architecture and initial training. a) The feedforward neural network is trained using the MNIST dataset with 50000, 1-bit, 28x28 pixel images using a batch size of 64, then validated and tested using 10000 images lecun_gradient-based_1998. The neural network is three layers with the input layer supporting 784 values for the 28x28 pixel images, the hidden layer supporting 50 neurons using a ReLU activation function, and the output layer supporting 10 neurons using a logarithmic softmax activation function to classify as a number. The neural network can map to the proposed neuromorphic photonic hardware that consists of 10 photonic cores with 50 rows of weight banks and 80 MRRs in each weight bank. Each core uses 80 wavelengths and 50 semiconductor optical amplifiers (SOA) to compensate for the splitting loss. b) The neural network achieves more than 95% inference accuracy after one epoch for all numbers. The specifics of the neural network architecture, and modeling are detailed in Methods.
• Figure 5: Neural network emulation results with and without non-idealities from the analog memory and system, such as control bit precision, noise, leakage, and latency. a) Minimum analog memory control bit precision to achieve more than 95% inference accuracy is 4 bits for weights trimmed only in inference and 8 bits for weights trimmed in inference and training. Inference accuracy degrades with increasing laser, SOA, PD, and TIA noise, but inference accuracy degrades b) earlier when weights are trained without noise and c) later when weights are trained with noise. d) The sweep of network latency and retention time characterizes inference accuracy for weights trained with and without leaky analog memory and network latency. Network latency and analog memory retention time constant at the point when inference accuracy degrades by 10% is plotted. When weights are trained with the effects of network latency and memory retention time, the network compensates for these effects and allows for a lower analog memory retention time constant requirement. Batch sizes of 64, 32, and 16 reveal that large batch sizes require longer retention times since weights are updated less frequently. Weights are updated more frequently in smaller batch sizes. The Supplementary Information expands on results in d).