Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems

TL;DR

This paper argues that the historical separation of concerns between DRAM producers and consumers is hindering progress on modern DRAM scaling. By examining four system-memory cooperation directions—latency reduction, refresh overheads, RowHammer defenses, and memory reliability—the authors identify consumer-access to reliability information as the principal bottleneck. They propose a two-step plan to address this: first, immediate information release through crowdsourcing and producer datasheets, and second, long-term DRAM standards that formalize reliability information sharing. The work highlights that enabling transparency can unlock new cross-domain innovations, improving performance, security, and reliability of DRAM-based systems in the face of slower technology scaling.

Abstract

Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns. To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

Figures (9)

• Figure 1: Semi-log plot showing the evolution of key DRAM access timings (left) and per-chip storage capacity (right)$^\mathrm{i}$ across each 5-year period of time.
• Figure 2: Refresh penalty (computed as the ratio between $t_{RFC}$ and $t_{REFI}$) for DRAM chips of different storage capacities.
• Figure 3: Flow of information necessary to determine key error characteristics for a given DRAM device.
• Figure 4: Evolution of four key DRAM timing parameters (shown in log scale) across years (top) and chip capacities (bottom) separated by DRAM standard.
• Figure 5: Evolution of the minimum, median, and maximum values of key DRAM timing parameters (shown in log scale) for each 5-year period (top) and DRAM standard (bottom).