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A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges

Xinchao Zhong, Sean Longyu Ma, Hong-fu Chou

TL;DR

The work tackles the bottlenecks of THz IoT transceivers, notably DAC linearity and the need for high-order modulation at terahertz frequencies. It proposes Modified PWM (MPWM) as a flexible, edge-efficient DAC paradigm and demonstrates its integration into a RISC-V based SoC, including FPGA validation and HR-MPWM enhancements. The paper provides a comprehensive treatment of MPWM theory, static/instructional error metrics, and dynamic performance, alongside architectural considerations for THz multi-antenna transceivers and antenna integration. The combined MPWM-DAC and RISC-V SoC design offers a pathway to energy-efficient, high-throughput THz IoT devices with practical FPGA/CMOS implementations.

Abstract

Terahertz (THz) communication is considered a viable approach to augmenting the communication capacity of prospective Internet-of-Things (IoT) resulting in enhanced spectral efficiency. This study first provides an outline of the design challenges encountered in developing THz transceivers. This paper introduces advanced approaches and a unique methodology known as Modified Pulse-width Modulation (MPWM) to address the issues in the THz domain. In this situation involving a transceiver that handles complex modulation schemes, the presence of a mixed signal through a high-resolution digital-to-analog converter (DAC) in the transmitter greatly contributes to the limitation in maintaining linearity at high frequencies. The utilization of Pulse-width Modulation-based Digital-to-Analog Converters (PWM-DACs) has garnered significant attention among scholars due to its efficiency and affordability. However, the converters' performance is restricted by insufficient conversion speed and precision, especially in the context of high-resolution, high-order modulation schemes for THz wireless communications. The MPWM framework offers a multitude of adjustable options, rendering the final MPWM-DAC highly adaptable for a diverse array of application scenarios. Comparative performance assessments indicate that MPWM-DACs have enhanced conversion speed compared to standard PWM-DACs, and they also provide greater accuracy in comparison to Pulse-count Modulation DACs (PCM-DACs). The study presents a comprehensive examination of the core principles, spectrum characteristics, and evaluation metrics, as well as the development and experimental validation of the MPWM method. Furthermore, we present a RISC-V System-on-Chip (SoC) that incorporates an MPWM-DAC, offering a highly favorable resolution for THz IoT communications.

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges

TL;DR

The work tackles the bottlenecks of THz IoT transceivers, notably DAC linearity and the need for high-order modulation at terahertz frequencies. It proposes Modified PWM (MPWM) as a flexible, edge-efficient DAC paradigm and demonstrates its integration into a RISC-V based SoC, including FPGA validation and HR-MPWM enhancements. The paper provides a comprehensive treatment of MPWM theory, static/instructional error metrics, and dynamic performance, alongside architectural considerations for THz multi-antenna transceivers and antenna integration. The combined MPWM-DAC and RISC-V SoC design offers a pathway to energy-efficient, high-throughput THz IoT devices with practical FPGA/CMOS implementations.

Abstract

Terahertz (THz) communication is considered a viable approach to augmenting the communication capacity of prospective Internet-of-Things (IoT) resulting in enhanced spectral efficiency. This study first provides an outline of the design challenges encountered in developing THz transceivers. This paper introduces advanced approaches and a unique methodology known as Modified Pulse-width Modulation (MPWM) to address the issues in the THz domain. In this situation involving a transceiver that handles complex modulation schemes, the presence of a mixed signal through a high-resolution digital-to-analog converter (DAC) in the transmitter greatly contributes to the limitation in maintaining linearity at high frequencies. The utilization of Pulse-width Modulation-based Digital-to-Analog Converters (PWM-DACs) has garnered significant attention among scholars due to its efficiency and affordability. However, the converters' performance is restricted by insufficient conversion speed and precision, especially in the context of high-resolution, high-order modulation schemes for THz wireless communications. The MPWM framework offers a multitude of adjustable options, rendering the final MPWM-DAC highly adaptable for a diverse array of application scenarios. Comparative performance assessments indicate that MPWM-DACs have enhanced conversion speed compared to standard PWM-DACs, and they also provide greater accuracy in comparison to Pulse-count Modulation DACs (PCM-DACs). The study presents a comprehensive examination of the core principles, spectrum characteristics, and evaluation metrics, as well as the development and experimental validation of the MPWM method. Furthermore, we present a RISC-V System-on-Chip (SoC) that incorporates an MPWM-DAC, offering a highly favorable resolution for THz IoT communications.
Paper Structure (22 sections, 15 equations, 17 figures, 1 table)

This paper contains 22 sections, 15 equations, 17 figures, 1 table.

Table of Contents

  1. Introduction
  2. High-throughput THz multi-antenna array design
  3. On-chip antennas
  4. off-chip antennas
  5. On-chip and off-chip antenna array
  6. THz multi-antenna transceivers Design
  7. High-performance multi-antenna systems
  8. Low-complexity MIMO precoding Designs
  9. High-speed high-resolution DAC for high order modulation
  10. Principle and spectrum of MPWM
  11. Performance of MPWM-DACs
  12. Static error
  13. Integral nonlinearity (INL)
  14. Differential nonlinearity (DNL)
  15. Dynamic Characteristics
  16. ...and 7 more sections

Figures (17)

  • Figure 1: The waveform of unfiltered MPWM digital output.
  • Figure 2: The spectrum of unfiltered MPWM digital output.
  • Figure 3: The MPWM generation using a 5-bit counter with 2 address bits.
  • Figure 4: The waveform of the output of Address Decoder and Data Decoder.
  • Figure 5: MPWM waveform in the case of Duty = 19, $SN_{pos}$ = 2, and Data = 4.
  • ...and 12 more figures