Log-Log Domain Sum-Product Algorithm for Information Reconciliation in Continuous-Variable Quantum Key Distribution

TL;DR

The paper tackles the hardware challenges of LDPC decoding in CV-QKD by introducing a log-log domain SPA that drastically reduces message precision. By deriving an approximate CN update, adopting log-LLR representations, and applying a fixed-point offset, the method achieves at least a 25% reduction in fractional bit width without increasing iterations or complexity. Results show that the log-log SPA attains decoding performance comparable to floating-point SPA and superior to fixed-point SPA, particularly for ultra-low-rate codes, while enabling smaller memory footprints. This approach offers a practical path to efficient, FPGA/ASIC-friendly information reconciliation in long-distance CV-QKD deployments, with broad implications for secure quantum communications.

Abstract

In this paper, we present a novel log-log domain sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes in continuous-variable quantum key distribution (CV-QKD) systems. This algorithm reduces the fractional bit width of decoder messages, leading to a smaller memory footprint and a lower resource consumption in hardware implementation. We also provide practical insights for fixed-point arithmetic and compare our algorithm with the conventional SPA in terms of performance and complexity. Our results show that our algorithm achieves comparable or better decoding accuracy than the conventional SPA while saving at least $25\%$ of the fractional bit width.

Figures (4)

• Figure 1: Protographs of the optimized TBP-LDPC codes 9562244 of rates (a) $R=0.01$ and (b) $R=0.1$. The (red) numbers at the lower right in the boxes represents the optimized repetition values for the subgraph in the box.
• Figure 2: Performance comparison of the SPA CN and the approximate CN update equations for the TBP-LDPC codes of rates (a) $R=0.01$ with $N=998400$ and (b) $R=0.1$ with $N=128000$
• Figure 3: Performance comparison of floating point sum-product algorithm (SPA), fixed point (FP) SPA and FP log-LLR decoding for the TBP-LDPC codes of rates $R=0.01$ with $N=998400$. FP(1,$x$,$y$) represents one sign bit, $x$ integer bits, $y$ fraction bits for FP representation.
• Figure 4: Performance comparison of floating point sum-product algorithm (SPA), fixed point (FP) SPA and FP log-LLR decoding for the TBP-LDPC code of rate $R=0.1$ with $N=128000$. FP(1,$x$,$y$) represents one sign bit, $x$ integer bits, $y$ fraction bits for FP representation.