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Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS

Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu

TL;DR

The paper tackles the mismatch between IR-level HLS timing estimates and post-synthesis QoR by introducing ISDC, a feedback-guided iterative SDC scheduling framework. ISDC augments the traditional SDC LP with low-level delays from downstream tools and uses two subgraph extraction strategies (fanout-driven and window-based) to drive a no-human-in-loop feedback loop. Through delay updating and an efficient reformulation, ISDC refines schedules over multiple iterations, achieving a notable 28.5% reduction in register usage on 17 XLS-based benchmarks, at the cost of increased scheduling time. The work demonstrates the value of cross-layer feedback in HLS and provides an open-source implementation to enable broader adoption and further exploration with co-optimization of HLS and logic synthesis.

Abstract

This paper proposes ISDC, a novel feedback-guided iterative system of difference constraints (SDC) scheduling algorithm for high-level synthesis (HLS). ISDC leverages subgraph extraction-based low-level feedback from downstream tools like logic synthesizers to iteratively refine HLS scheduling. Technical innovations include: (1) An enhanced SDC formulation that effectively integrates low-level feedback into the linear-programming (LP) problem; (2) A fanout and window-based subgraph extraction mechanism driving the feedback cycle; (3) A no-human-in-loop ISDC flow compatible with a wide range of downstream tools and process design kits (PDKs). Evaluation shows that ISDC reduces register usage by 28.5% against an industrial-strength open-source HLS tool.

Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS

TL;DR

The paper tackles the mismatch between IR-level HLS timing estimates and post-synthesis QoR by introducing ISDC, a feedback-guided iterative SDC scheduling framework. ISDC augments the traditional SDC LP with low-level delays from downstream tools and uses two subgraph extraction strategies (fanout-driven and window-based) to drive a no-human-in-loop feedback loop. Through delay updating and an efficient reformulation, ISDC refines schedules over multiple iterations, achieving a notable 28.5% reduction in register usage on 17 XLS-based benchmarks, at the cost of increased scheduling time. The work demonstrates the value of cross-layer feedback in HLS and provides an open-source implementation to enable broader adoption and further exploration with co-optimization of HLS and logic synthesis.

Abstract

This paper proposes ISDC, a novel feedback-guided iterative system of difference constraints (SDC) scheduling algorithm for high-level synthesis (HLS). ISDC leverages subgraph extraction-based low-level feedback from downstream tools like logic synthesizers to iteratively refine HLS scheduling. Technical innovations include: (1) An enhanced SDC formulation that effectively integrates low-level feedback into the linear-programming (LP) problem; (2) A fanout and window-based subgraph extraction mechanism driving the feedback cycle; (3) A no-human-in-loop ISDC flow compatible with a wide range of downstream tools and process design kits (PDKs). Evaluation shows that ISDC reduces register usage by 28.5% against an industrial-strength open-source HLS tool.
Paper Structure (22 sections, 3 equations, 8 figures, 1 table, 2 algorithms)

This paper contains 22 sections, 3 equations, 8 figures, 1 table, 2 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Iterative SDC Scheduling
  4. Overall Flow
  5. Why low-level feedback helps
  6. Why an iterative approach helps
  7. Subgraph Extraction Strategy
  8. Fanout-driven strategy
  9. Window-based strategy
  10. Delay Updating
  11. SDC Reformulation
  12. Evaluation
  13. Ablation Study
  14. Fanout-driven strategy
  15. Window-based strategy
  16. ...and 7 more sections

Figures (8)

  • Figure 1: Post-synthesis STA vs. XLS-estimated critical path delay of 6912 different HLS design points.
  • Figure 2: Overall flow of ISDC scheduling algorithm.
  • Figure 3: Delay-based vs. fanout-based subgraph extraction.
  • Figure 4: Cone-based vs. window-based subgraph extraction.
  • Figure 5: Ablation study of delay-driven and fanout-driven subgraph extraction. Path-based strategy is used.
  • ...and 3 more figures