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Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks

Shashwat Khandelwal, Anneliese Walsh, Shanker Shreejith

TL;DR

The paper addresses security gaps in automotive CAN networks and the challenge of embedding ML-based IDS within power- and latency-constrained ECUs. It proposes a custom quantised MLP IDS implemented as an IP block on a Zynq Ultrascale+ FPGA, trained with FINN quantisation-aware training on the Car Hacking dataset, with 4-bit uniform quantisation chosen after design-space exploration. The evaluated results show near-line-rate performance with 0.12 ms per CAN frame, 0.25 mJ per inference, throughput above 8300 messages per second, and power around 2.09 W, while maintaining competitive detection metrics. Compared with GPU- and CPU-based IDS approaches, the FPGA-based solution delivers substantial reductions in latency and energy, and supports multiple concurrent models within a single ECU, enabling scalable, low-power IDS deployment in automotive networks.

Abstract

In this paper, we explore low-power custom quantised Multi-Layer Perceptrons (MLPs) as an Intrusion Detection System (IDS) for automotive controller area network (CAN). We utilise the FINN framework from AMD/Xilinx to quantise, train and generate hardware IP of our MLP to detect denial of service (DoS) and fuzzying attacks on CAN network, using ZCU104 (XCZU7EV) FPGA as our target ECU architecture with integrated IDS capabilities. Our approach achieves significant improvements in latency (0.12 ms per-message processing latency) and inference energy consumption (0.25 mJ per inference) while achieving similar classification performance as state-of-the-art approaches in the literature.

Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks

TL;DR

The paper addresses security gaps in automotive CAN networks and the challenge of embedding ML-based IDS within power- and latency-constrained ECUs. It proposes a custom quantised MLP IDS implemented as an IP block on a Zynq Ultrascale+ FPGA, trained with FINN quantisation-aware training on the Car Hacking dataset, with 4-bit uniform quantisation chosen after design-space exploration. The evaluated results show near-line-rate performance with 0.12 ms per CAN frame, 0.25 mJ per inference, throughput above 8300 messages per second, and power around 2.09 W, while maintaining competitive detection metrics. Compared with GPU- and CPU-based IDS approaches, the FPGA-based solution delivers substantial reductions in latency and energy, and supports multiple concurrent models within a single ECU, enabling scalable, low-power IDS deployment in automotive networks.

Abstract

In this paper, we explore low-power custom quantised Multi-Layer Perceptrons (MLPs) as an Intrusion Detection System (IDS) for automotive controller area network (CAN). We utilise the FINN framework from AMD/Xilinx to quantise, train and generate hardware IP of our MLP to detect denial of service (DoS) and fuzzying attacks on CAN network, using ZCU104 (XCZU7EV) FPGA as our target ECU architecture with integrated IDS capabilities. Our approach achieves significant improvements in latency (0.12 ms per-message processing latency) and inference energy consumption (0.25 mJ per inference) while achieving similar classification performance as state-of-the-art approaches in the literature.
Paper Structure (2 sections, 1 figure, 2 tables)

This paper contains 2 sections, 1 figure, 2 tables.

Table of Contents

  1. Introduction & Proposed Architecture
  2. Results & Conclusion

Figures (1)

  • Figure 1: System diagram of the CAN network (featuring components connected to high/low speed CAN) incorporating ECUs capable of intrusion detection.