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Study on the Particle Sorting Performance for Reactor Monte Carlo Neutron Transport on Apple Unified Memory GPUs

Changyuan Liu

TL;DR

The finding is that for the Apple M2 max and M3 max chip, sorting on CPU leads to better performance per power than sorting on GPU for the ExaSMR whole core benchmark problems and the HTR-10 high temperature gas reactor fuel pebble problem.

Abstract

In simulation of nuclear reactor physics using the Monte Carlo neutron transport method on GPUs, the sorting of particles plays a significant role in performance of calculation. Traditionally, CPUs and GPUs are separated devices connected at low data transfer rate and high data transfer latency. Emerging computing chips tend to integrate CPUs and GPUs. One example is the Apple silicon chips with unified memory. Such unified memory chips have opened doors for new strategies of collaboration between CPUs and GPUs for Monte Carlo neutron transport. Sorting particle on CPU and transport on GPU is an example of such new strategy, which has been suffering the high CPU-GPU data transfer latency on the traditional devices with separated CPU and GPU. The finding is that for the Apple M2 max chip, sorting on CPU leads to better performance per power than sorting on GPU for the ExaSMR whole core benchmark problems and the HTR-10 high temperature gas reactor fuel pebble problem. The partially sorted particle order has been identified to contribute to the higher performance with CPU sort than GPU. The in-house code using both CPU and GPU achieves 7.5 times power efficiency that of OpenMC on CPU for ExaSMR whole core benchmark with depleted fuel, and 150 times for HTR-10 fuel pebble benchmark with depleted fuel.

Study on the Particle Sorting Performance for Reactor Monte Carlo Neutron Transport on Apple Unified Memory GPUs

TL;DR

The finding is that for the Apple M2 max and M3 max chip, sorting on CPU leads to better performance per power than sorting on GPU for the ExaSMR whole core benchmark problems and the HTR-10 high temperature gas reactor fuel pebble problem.

Abstract

In simulation of nuclear reactor physics using the Monte Carlo neutron transport method on GPUs, the sorting of particles plays a significant role in performance of calculation. Traditionally, CPUs and GPUs are separated devices connected at low data transfer rate and high data transfer latency. Emerging computing chips tend to integrate CPUs and GPUs. One example is the Apple silicon chips with unified memory. Such unified memory chips have opened doors for new strategies of collaboration between CPUs and GPUs for Monte Carlo neutron transport. Sorting particle on CPU and transport on GPU is an example of such new strategy, which has been suffering the high CPU-GPU data transfer latency on the traditional devices with separated CPU and GPU. The finding is that for the Apple M2 max chip, sorting on CPU leads to better performance per power than sorting on GPU for the ExaSMR whole core benchmark problems and the HTR-10 high temperature gas reactor fuel pebble problem. The partially sorted particle order has been identified to contribute to the higher performance with CPU sort than GPU. The in-house code using both CPU and GPU achieves 7.5 times power efficiency that of OpenMC on CPU for ExaSMR whole core benchmark with depleted fuel, and 150 times for HTR-10 fuel pebble benchmark with depleted fuel.
Paper Structure (19 sections, 8 figures, 10 tables)

This paper contains 19 sections, 8 figures, 10 tables.

Table of Contents

  1. Introduction
  2. Development on Apple Silicon as a Unified Memory Device
  3. Apple M2 Max Chip
  4. Objective-C/Swift Programming Languages and Frameworks
  5. Metal Shading Language & Framework
  6. Apple GPU Programming Patterns
  7. Sorting Algorithms
  8. Summary of Sorting Algorithms on CPU & GPU
  9. Performance of Sorting on Apple Chip
  10. Random Integers
  11. Partially Sorted Integers
  12. Sorting Strategy for Monte Carlo Neutron Transport
  13. Reactor Simulation Benchmarks
  14. Simulation Configuration
  15. Verification: VERA Pincell & Assembly Benchmark Problem
  16. ...and 4 more sections

Figures (8)

  • Figure 1: A snapshot of the design of some recent merged CPU and GPU chips .
  • Figure 2: A snapshot apple_m2max (left) and a sketch of the design (right) of Apple M2 Max chip. I-Cache stands for instruction cache, and D-Cache stands for data cache. Avalanche and Blizzard are architecture design code names.
  • Figure 3: A sketch of application development in Objective-C & Swift programming language on Apple devices.
  • Figure 4: A sketch of CPU-GPU program compilation scheme on Nvidia and Apple GPU devices.
  • Figure 5: Programming patterns for Apple GPU.
  • ...and 3 more figures