Quantum circuit model for discrete-time three-state quantum walks on Cayley graphs

TL;DR

This work develops qutrit-circuit models for discrete-time three-state quantum walks on Cayley graphs of Dihedral and cyclic groups, enabling implementation with a gate set of qutrit rotations, qutrit-X, and two-qutrit controlled-X operations. A key theoretical contribution is a scalable decomposition of any $3\times3$ SU(3) coin gate into qutrit-rotation gates, together with circuit constructions for both $\mathrm{Cay(D_N,\{a,b\})}$ and lively $\mathrm{Cay({\mathbb Z}_N,\{1,-1\})}$ walks, including handling of cases where $N$ is not a power of three. The authors further present a scalable, ancilla-free method to realize $3\times3$ block-diagonal unitaries via multi-controlled qutrit gates, and derive explicit circuit-complexity results. Numerical noisy simulations using Kraus-based gate and idle errors quantify how gate noise dominates distributional deviations in time-averaged walker probabilities, offering practical guidance for qutrit-based DTQW experiments and circuit design. These results bridge theoretical DTQW models and hardware-aware quantum circuit implementations, highlighting robustness considerations for qudit-based quantum algorithms.

Abstract

We develop qutrit circuit models for discrete-time three-state quantum walks on Cayley graphs corresponding to Dihedral groups $D_N$ and the additive groups of integers modulo any positive integer $N$. The proposed circuits comprise of elementary qutrit gates such as qutrit rotation gates, qutrit-$X$ gates and two-qutrit controlled-$X$ gates. First, we propose qutrit circuit representation of special unitary matrices of order three, and the block diagonal special unitary matrices with $3\times 3$ diagonal blocks, which correspond to multi-controlled $X$ gates and permutations of qutrit Toffoli gates. We show that one-layer qutrit circuit model need $O(3nN)$ two-qutrit control gates and $O(3N)$ one-qutrit rotation gates for these quantum walks when $N=3^n$. Finally, we numerically simulate these circuits to mimic its performance such as time-averaged probability of finding the walker at any vertex on noisy quantum computers. The simulated results for the time-averaged probability distributions for noisy and noiseless walks are further compared using KL-divergence and total variation distance. These results show that noise in gates in the circuits significantly impacts the distributions than amplitude damping or phase damping errors.

Figures (9)

• Figure 1: $\mathrm{Cay(\mathbb{Z}_4,\{1,-1\})}$ (left) and $\mathrm{Cay(D_4,\{a,b\})}$ (right)
• Figure 2: Time averaged probability for $\mathrm{Cay(D_{27},\{a,b\})}$ taking coins from the classes $,\mathcal{X}_\theta,\mathcal{Y}_\theta,\mathcal{Z}_\theta,\mathcal{W}_\theta$ with initial position $(1,0)$ and initial coin state $\ket{0}_3$. The time step is taken up to $300$. The generic depolarizer gate noise and amplitude damping idle noise is incorporated in the circuit.
• Figure 3: Time averaged probability for $\mathrm{Cay(D_{27},\{a,b\})}$ taking coins from the classes $,\mathcal{X}_\theta,\mathcal{Y}_\theta,\mathcal{Z}_\theta,\mathcal{W}_\theta$ with initial position $(1,0)$ and initial coin state $\ket{0}_3$. The time step is taken up to $300$. The generic depolarizer gate noise and phase damping idle noise is incorporated in the circuit. The error parameters are chosen from uniform distribution.
• Figure 4: Time averaged probability for $\mathrm{Cay(\mathbb{Z}_{27},\{1,-1\})}$ taking coins from the classes $,\mathcal{X}_\theta,\mathcal{Y}_\theta,\mathcal{Z}_\theta,\mathcal{W}_\theta$ with initial position $0$ and initial coin state $\frac{1}{\sqrt{3}}(\ket{0}_3+\ket{1}_3+\ket{2}_3)$. The time step is taken up to $300$. The generic depolarizer gate noise and amplitude damping idle noise is incorporated in the circuit. The error parameters are chosen from uniform distribution.
• Figure 5: Time averaged probability for $\mathrm{Cay(\mathbb{Z}_{27},\{1,-1\})}$ taking coins from the classes $,\mathcal{X}_\theta,\mathcal{Y}_\theta,\mathcal{Z}_\theta,\mathcal{W}_\theta$ with initial position $0$ and initial coin state $\frac{1}{\sqrt{3}}(\ket{0}_3+\ket{1}_3+\ket{2}_3)$. The time step is taken up to $300$. The generic depolarizer gate noise and phase damping idle noise is incorporated in the circuit. The error parameters are chosen from the uniform distribution.