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An Energy-efficient Capacitive-RRAM Content Addressable Memory

Yihan Pan, Adrian Wheeldon, Mohammed Mughal, Shady Agwa, Themis Prodromakis, Alexantrou Serb

TL;DR

The paper tackles the high energy cost of traditional CAMs by introducing a capacitive-divider based 3T1R1C TCAM that performs content-addressable search in the charge domain, thereby eliminating DC paths. It combines an in-house modeled RRAM (Au/TiO2/Pt) with a bottom capacitor to create a tunable capacitive divider that modulates the match-line during search, enabling energy-efficient parallel operation in a 64×64 array at 875 MHz in 0.18 µm technology. Key contributions include a complete circuit-level design of the CAM cell, a data-driven RRAM model, an integrated system with CAR/AAR/WRT support, and measured energy and timing metrics (e.g., 1.71 fJ/bit-search for matches and 4.69 fJ/bit-search for misses). The work demonstrates substantial energy savings relative to DC-path CAMs and highlights practical considerations for scaling, PVT variation, and peripheral energy, pointing to viable campus- and data-center-level deployments of energy-efficient in-memory associative memory.

Abstract

Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a 64 x 64 array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.

An Energy-efficient Capacitive-RRAM Content Addressable Memory

TL;DR

The paper tackles the high energy cost of traditional CAMs by introducing a capacitive-divider based 3T1R1C TCAM that performs content-addressable search in the charge domain, thereby eliminating DC paths. It combines an in-house modeled RRAM (Au/TiO2/Pt) with a bottom capacitor to create a tunable capacitive divider that modulates the match-line during search, enabling energy-efficient parallel operation in a 64×64 array at 875 MHz in 0.18 µm technology. Key contributions include a complete circuit-level design of the CAM cell, a data-driven RRAM model, an integrated system with CAR/AAR/WRT support, and measured energy and timing metrics (e.g., 1.71 fJ/bit-search for matches and 4.69 fJ/bit-search for misses). The work demonstrates substantial energy savings relative to DC-path CAMs and highlights practical considerations for scaling, PVT variation, and peripheral energy, pointing to viable campus- and data-center-level deployments of energy-efficient in-memory associative memory.

Abstract

Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a 64 x 64 array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.
Paper Structure (12 sections, 1 equation, 18 figures, 4 tables)

This paper contains 12 sections, 1 equation, 18 figures, 4 tables.

Table of Contents

  1. Introduction
  2. RRAM model
  3. System Overview
  4. 3T1R1C CAM cell
  5. System
  6. Layout
  7. Measurements
  8. Function and Timing
  9. Energy
  10. Corners
  11. Discussion
  12. Conclusion

Figures (18)

  • Figure 1:
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  • Figure 6:
  • ...and 13 more figures