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On Optimization of Next-Generation Microservice-Based Core Networks

Andrea Tassi, Daniel Warren, Yue Wang, Deval Bhamare, Rasoul Behravesh

TL;DR

The authors address optimizing control-plane processing for a microservice-based 5G core by partitioning and mapping large MS graphs onto heterogeneous bare-metal deployments to minimize inter-server traffic. They formulate a Core Optimization problem and develop a practical MM heuristic to compute feasible, near-optimal allocations. Empirical results show MS-based cores robustly support requested CP loads with lower inter-server traffic than NF- or procedure-based architectures, particularly as server heterogeneity increases. The work demonstrates scalable traffic-aware MS placement and highlights potential for dynamic re-optimization as network loads evolve.

Abstract

Next-generation mobile core networks are required to be scalable and capable of efficiently utilizing heterogeneous bare metal resources that may include edge servers. To this end, microservice-based solutions where control plane procedures are deconstructed in their fundamental building blocks are gaining momentum. This letter proposes an optimization framework delivering the partitioning and mapping of large-scale microservice graphs onto heterogeneous bare metal deployments while minimizing the total network traffic among servers. An efficient heuristic strategy for solving the optimization problem is also provided. Simulation results show that, with the proposed framework, a microservice-based core can consistently support the requested load in heterogeneous bare metal deployments even when alternative architecture fails. Besides, our framework ensures an overall reduction in the control plane-related network traffic if compared to current core architectures.

On Optimization of Next-Generation Microservice-Based Core Networks

TL;DR

The authors address optimizing control-plane processing for a microservice-based 5G core by partitioning and mapping large MS graphs onto heterogeneous bare-metal deployments to minimize inter-server traffic. They formulate a Core Optimization problem and develop a practical MM heuristic to compute feasible, near-optimal allocations. Empirical results show MS-based cores robustly support requested CP loads with lower inter-server traffic than NF- or procedure-based architectures, particularly as server heterogeneity increases. The work demonstrates scalable traffic-aware MS placement and highlights potential for dynamic re-optimization as network loads evolve.

Abstract

Next-generation mobile core networks are required to be scalable and capable of efficiently utilizing heterogeneous bare metal resources that may include edge servers. To this end, microservice-based solutions where control plane procedures are deconstructed in their fundamental building blocks are gaining momentum. This letter proposes an optimization framework delivering the partitioning and mapping of large-scale microservice graphs onto heterogeneous bare metal deployments while minimizing the total network traffic among servers. An efficient heuristic strategy for solving the optimization problem is also provided. Simulation results show that, with the proposed framework, a microservice-based core can consistently support the requested load in heterogeneous bare metal deployments even when alternative architecture fails. Besides, our framework ensures an overall reduction in the control plane-related network traffic if compared to current core architectures.
Paper Structure (6 sections, 5 equations, 3 figures, 1 table, 1 algorithm)

This paper contains 6 sections, 5 equations, 3 figures, 1 table, 1 algorithm.

Table of Contents

  1. Introduction
  2. System Model
  3. Proposed Optimization Framework
  4. Proposed MS Mapping Procedure
  5. Analytical Results
  6. Conclusions

Figures (3)

  • Figure 1: Average cost difference as a function of the total number of MS instances to be mapped onto the available servers. The average CBC and MM procedure completion times have been measured on a workstation equipped with a CPU AMD 5995WX. Legend of both figures is reported in Fig. \ref{['fig.1.1']}.
  • Figure 2: Maximum number of instances and cost as a function of $|\mathcal{S}|$, for multiple requested loads, in the case of MS-, NF- and procedure-based architectures. Legend of all figures is reported in Fig. \ref{['fig.2.4']}.
  • Figure 3: Allocated bare metal resources (CPU or memory) as a function of $\hat{U}$, for MS-based and multi-threaded NF- and procedure-based architectures.

Theorems & Definitions (2)

  • Remark 2.1
  • Remark 4.1