MicroNAS: Zero-Shot Neural Architecture Search for MCUs

TL;DR

MicroNAS tackles the expensive neural architecture search problem for MCUs by introducing a hardware-aware zero-shot NAS framework that uses a hybrid objective combining the Spectrum of Neural Tangent Kernel (NTK), Linear Region Count, and hardware proxies. It includes a hardware-aware pruning-based search and a latency estimator to predict MCU inference latency without full training. In experiments on NAS-Bench-201 and an STM32 MCU, MicroNAS achieves up to $1104\times$ search efficiency and models with over $3.23\times$ faster MCU inference while maintaining similar accuracy, outperforming prior methods like TE-NAS and muNAS. This work enables practical, energy-efficient neural architecture search for edge devices.

Abstract

Neural Architecture Search (NAS) effectively discovers new Convolutional Neural Network (CNN) architectures, particularly for accuracy optimization. However, prior approaches often require resource-intensive training on super networks or extensive architecture evaluations, limiting practical applications. To address these challenges, we propose MicroNAS, a hardware-aware zero-shot NAS framework designed for microcontroller units (MCUs) in edge computing. MicroNAS considers target hardware optimality during the search, utilizing specialized performance indicators to identify optimal neural architectures without high computational costs. Compared to previous works, MicroNAS achieves up to 1104x improvement in search efficiency and discovers models with over 3.23x faster MCU inference while maintaining similar accuracy

Figures (2)

• Figure 1: Overview of Proposed MicroNAS Workflow
• Figure 2: Kendall-$\tau$ vs Batch Size, Condition Number $K_i$