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Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs

Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo

TL;DR

This work tackles the slow turnaround in FPGA HLS when evaluating post-route QoR by introducing a hierarchical GNN framework that predicts latency and resource usage directly from C/C++ source code without invoking the full design flow. It constructs pragma-aware graphs from CDFGs via an extended PrograML-based pipeline, extracts rich node and loop-level features, and trains separate GNNs for inner (pipelined vs non-pipelined) loops and an outer graph to predict full application QoR. The approach achieves less than 10% prediction error across QoR metrics and significantly accelerates design space exploration, reducing it from days to minutes with an average ADRS of 6.91% on unseen designs. This method demonstrates a practical, scalable path to fast QoR feedback, enabling efficient DSE for FPGA HLS and guiding pragma configurations for optimal performance.

Abstract

High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route quality of results (QoR) are considered during optimization. To tackle this issue, we propose a hierarchical post-route QoR prediction approach for FPGA HLS, which features: (1) a modeling flow that directly estimates latency and post-route resource usage from C/C++ programs; (2) a graph construction method that effectively represents the control and data flow graph of source code and effects of HLS pragmas; and (3) a hierarchical GNN training and prediction method capable of capturing the impact of loop hierarchies. Experimental results show that our method presents a prediction error of less than 10% for different types of QoR metrics, which gains tremendous improvement compared with the state-of-the-art GNN methods. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91% on average.

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs

TL;DR

This work tackles the slow turnaround in FPGA HLS when evaluating post-route QoR by introducing a hierarchical GNN framework that predicts latency and resource usage directly from C/C++ source code without invoking the full design flow. It constructs pragma-aware graphs from CDFGs via an extended PrograML-based pipeline, extracts rich node and loop-level features, and trains separate GNNs for inner (pipelined vs non-pipelined) loops and an outer graph to predict full application QoR. The approach achieves less than 10% prediction error across QoR metrics and significantly accelerates design space exploration, reducing it from days to minutes with an average ADRS of 6.91% on unseen designs. This method demonstrates a practical, scalable path to fast QoR feedback, enabling efficient DSE for FPGA HLS and guiding pragma configurations for optimal performance.

Abstract

High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route quality of results (QoR) are considered during optimization. To tackle this issue, we propose a hierarchical post-route QoR prediction approach for FPGA HLS, which features: (1) a modeling flow that directly estimates latency and post-route resource usage from C/C++ programs; (2) a graph construction method that effectively represents the control and data flow graph of source code and effects of HLS pragmas; and (3) a hierarchical GNN training and prediction method capable of capturing the impact of loop hierarchies. Experimental results show that our method presents a prediction error of less than 10% for different types of QoR metrics, which gains tremendous improvement compared with the state-of-the-art GNN methods. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91% on average.
Paper Structure (22 sections, 2 equations, 4 figures, 5 tables)

This paper contains 22 sections, 2 equations, 4 figures, 5 tables.

Table of Contents

  1. Introduction
  2. PRELIMINARIES
  3. Control and Data Flow Graph (CDFG)
  4. Graph Neural Network
  5. Methodology
  6. Graph Construction
  7. Constructing graph with loop pipelining
  8. Constructing graph with loop unrolling
  9. Constructing graph with array partitioning
  10. Feature Extraction and Annotation
  11. Node Features
  12. Loop-level features
  13. The Hierarchical Modeling Approach
  14. Inner Hierarchy
  15. Outer Hierarchy
  16. ...and 7 more sections

Figures (4)

  • Figure 1: Framework overview
  • Figure 2: Procedure of graph construction.
  • Figure 3: The illustration of our hierarchical source-to-post-route QoR modeling approach.
  • Figure 4: GNN architectures and the corresponding hierarchical training process.