Conditional Flood Fill Method in Logic Synthesis
Shitian Yang, Junyue Jiang, Yilai Liang, Xiaoyang Chu
TL;DR
The paper tackles scalability and efficiency challenges in logic synthesis where traditional minimization methods like Quine–McCluskey and Espresso struggle for higher-dimensional Boolean functions. It introduces a heuristic, the Conditional Flood Fill method, based on a count-based adjacency framework and flood-fill expansion, guided by nine theorems to identify implicants. Key contributions include the nine theorems, a complete single-output SOP algorithm, and experimental evidence of substantial improvements in computational speed and memory efficiency, with extensions to multi-output through output consolidation. The approach offers a practical, non-approximate path to simplifying Boolean functions, enabling faster upfront optimization in circuit design and potentially enhancing subsequent logic reduction stages in EDA workflows.
Abstract
In the field of Electronic Design Automation (EDA), logic synthesis plays a pivotal role in optimizing hardware resources. Traditional logic synthesis algorithms, such as the Quine-McCluskey method, face challenges in scalability and efficiency, particularly for higher-dimension problems. This paper introduces a novel heuristic algorithm based on Conditional Flood Fill Method aimed at addressing these limitations. Our method employs count-based adjacent element handling and introduces nine new theorems to guide the logic synthesis process. Experimental results validate the efficacy of our approach, showing significant improvements in computational efficiency and scalability compared to existing algorithms. The algorithm holds potential for future advancements in circuit development and Boolean function optimization.