A Dynamic Capacitance Matching (DCM)-based Current Response Algorithm for Signal Line RC Network

TL;DR

This work tackles the challenge of predicting signal-line current waveforms in RC interconnects without SPICE by introducing Dynamic Capacitance Matching (DCM). The method couples high-order driving-point models with a pre-characterized driver library through symbolic expressions to determine a time-varying effective capacitance $C_{eff}(t)$ that guides current predictions via $I(t) = C_{eff}\,\frac{dV}{dt}$. Key contributions include representing the RC load as a superposition of fixed-capacitance responses, employing piecewise-linear VPWL excitations, and using moment matching to obtain $Y(s)$ with a binary-search refinement over $C_{eff}$ to match the driver’s behavior, including overshoot/undershoot. Experimental results on a 40 nm CMOS process show near 1% accuracy in AVG, RMS, and peak currents with substantial speedups (50–200×) over NGSPICE, underscoring the method’s practicality for delay, power, and electromigration analyses.

Abstract

This paper proposes a dynamic capacitance matching (DCM)-based RC current response algorithm for calculating the current waveform of a signal line without performing SPICE simulation. Specifically, unlike previous method such as CCS model, driver linear representation, waveform functional fitting or equivalent load capacitance, our algorithm does not rely on fixed reduced model of both standard cell driver and RC load. Instead, our algorithm approaches the current waveform dynamically by computing current responses of the target driver for various load scenarios. Besides, we creatively use symbolic expression to combine the y-parameter of RC network with the pre-characterized driver library in order to perform capacitance matching by considering over/under-shoot effect. Our algorithm is experimentally verified on 40nm CMOS technology and has been partially adopted by latest commercial tool for other nodes. Experimental results show that our algorithm has excellent resolution and promising efficiency compared with traditional methods and SPICE golden result, especially for application in computing delay, power and signal line electromigration.

Figures (10)

• Figure 1: Limitations of traditional algorithms for RC modeling of signal lines.
• Figure 2: High level view of the proposed approach. Replace the driver and its input with the voltage curve interpolated from the driver characterization library.
• Figure 3: Voltage versus time plane. The black curves are interpolated from data library as the output voltage responses for different capacitance values of a specific driver (Eg: 0.01 pF to 0.05 pF). The red dashed line is the actual voltage response of an RC circuit crossing the black lines at different points.
• Figure 4: Searching the effective capacitance for each voltage step based on the driver characterization table.
• Figure 5: A (DCM)-based model.