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Preserving Power Optimizations Across the High Level Synthesis of Distinct Application-Specific Circuits

Paulo Garcia

TL;DR

The paper addresses preserving power optimizations across high-level synthesis by introducing an interpretation-based design flow that operates at a higher level of abstraction. It defines a formal HLS translation framework and a power estimation model that decomposes power into static and dynamic components while accounting for routing costs, enabling reuse of optimizations across different accelerator designs. Through experiments on two robotics-oriented accelerators using the Bambu HLS flow and post-synthesis power analysis, the authors demonstrate predictions within +/- 1% of measured values and show significant power reductions with optimizations such as loop perforation and arithmetic reduction. This work provides a practical pathway to integrate low-power concerns into early design stages, potentially improving design reuse and efficiency in FPGA-based accelerators.

Abstract

We evaluate the use of software interpretation to push High Level Synthesis of application-specific accelerators toward a higher level of abstraction. Our methodology is supported by a formal power consumption model that computes the power consumption of accelerator components, accurately predicting the power consumption on new designs from prior optimization estimations. We demonstrate how our approach simplifies the re-use of power optimizations across distinct designs, by leveraging the higher level of design abstraction, using two accelerators representative of the robotics domain, implemented through the Bambu High Level Synthesis tool. Results support the research hypothesis, achieving predictions accurate within +/- 1%.

Preserving Power Optimizations Across the High Level Synthesis of Distinct Application-Specific Circuits

TL;DR

The paper addresses preserving power optimizations across high-level synthesis by introducing an interpretation-based design flow that operates at a higher level of abstraction. It defines a formal HLS translation framework and a power estimation model that decomposes power into static and dynamic components while accounting for routing costs, enabling reuse of optimizations across different accelerator designs. Through experiments on two robotics-oriented accelerators using the Bambu HLS flow and post-synthesis power analysis, the authors demonstrate predictions within +/- 1% of measured values and show significant power reductions with optimizations such as loop perforation and arithmetic reduction. This work provides a practical pathway to integrate low-power concerns into early design stages, potentially improving design reuse and efficiency in FPGA-based accelerators.

Abstract

We evaluate the use of software interpretation to push High Level Synthesis of application-specific accelerators toward a higher level of abstraction. Our methodology is supported by a formal power consumption model that computes the power consumption of accelerator components, accurately predicting the power consumption on new designs from prior optimization estimations. We demonstrate how our approach simplifies the re-use of power optimizations across distinct designs, by leveraging the higher level of design abstraction, using two accelerators representative of the robotics domain, implemented through the Bambu High Level Synthesis tool. Results support the research hypothesis, achieving predictions accurate within +/- 1%.
Paper Structure (10 sections, 7 equations, 4 figures, 3 tables, 18 algorithms)

This paper contains 10 sections, 7 equations, 4 figures, 3 tables, 18 algorithms.

Table of Contents

  1. Introduction
  2. Related Work
  3. The High Level Synthesis Model
  4. Extant models
  5. Our contribution: modeling higher level interpretation
  6. Our contribution: power estimation
  7. Experiments and Results
  8. Formal description of prototypes
  9. Results
  10. Conclusions

Figures (4)

  • Figure 1: Extant High Level Synthesis flow: power optimizations depicted in blue.
  • Figure 2: This paper's contribution: moving the design towards a higher level of abstraction.
  • Figure 3: "Chaser" block diagram.
  • Figure 4: "Grabber" block diagram.