A Joint Optimization of Buffer and Splitter Insertion for Phase-Skipping Adiabatic Quantum-Flux-Parametron Circuits

TL;DR

The paper addresses the high buffer and splitter overhead in phase-skipping AQFP circuits by introducing an iterative optimization framework that couples phase-skipping aware level assignment with a phase-skipping optimized splitter-tree. The method combines an LP/ILP-based level solver with a phase-skipping DP splitter-tree and slack handling, iterating to improve global cost while maintaining feasible netlists. Empirical results show substantial improvements, including up to $74.1\%$ total buffer/splitter savings and up to $60\%$ JJ-count reduction on large nets, across 1–4 phase-skipping configurations. This work advances practical deployment of phase-skipping AQFP by delivering substantial area efficiency gains and informing future EDA tooling for superconducting logic.

Abstract

Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer requires connected gates to have shifted but overlapping clocks. As a result, buffers need to be used to balance re-convergent logic paths, a problem that is exacerbated by every multi-node fanout needing a tree of clocked splitters. Recent AQFP circuit design techniques have offered an opportunity to reduce buffer costs by supporting a notion of phase-skipping but the EDA support for these advanced circuits is limited. This paper proposes the first algorithm to optimize buffer and splitter insertion for phase-skipping AQFP circuits and achieves over 31\% savings over existing buffer reduction schemes and up to 74\% savings in buffers and splitter costs over the SOTA non-phase skipping circuits.

Figures (4)

• Figure 1: Circuit Construction of AQFP Buffer. Current directions shown for when flux is in the left loop, corresponding to a logical "1".
• Figure 2: Example clock routing and waveforms for (a) 4-Phase and (b) n-Phase schemes (n=8). Shaded area illustrates that for 8-phase clocking $\phi_0$ has equivalent overlap with $\phi_2$ as with $\phi_1$ in 4-Phase, allowing a phase skip and the associated reduction in inserted buffer cells. In (b) Phase-Skipping aware phase assignment of logic cells reduces inserted buffer costs.
• Figure 3: Example Flow of Proposed Iterative Algorithm
• Figure 4: Example of splitter tree subtree constructions for phase-skipping of 1 with a splitter fanout of 2.