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CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks

Levent Aksoy, Muhammad Yasin, Samuel Pagliarini

TL;DR

This paper tackles the vulnerability of existing logic locking to structural analysis by introducing CAC 2.0, an enhanced multi-flip locking approach. CAC 2.0 combines Double CAC with obfuscation of protected primary inputs to massively expand the attack surface a structural-analysis adversary must explore, while maintaining resilience to SAT-based and removal attacks. The authors implement CAC 2.0 and other techniques in the open-source HIID tool, demonstrate substantial, circuit-dependent hardware overhead, and show empirical resilience against a broad set of OL and OG attacks. The work provides a practical, auditable path to stronger IP protection in RTL pipelines, with clear trade-offs between security gain and area/power impact.

Abstract

Logic locking proposed to protect integrated circuits from serious hardware threats has been studied extensively over a decade. In these years, many efficient logic locking techniques have been proven to be broken. The state-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks, but vulnerable to structural analysis attacks. To overcome this drawback, this paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. To do so, CAC 2.0 locks the original circuit twice, one after another, on different nodes with different number of protected primary inputs using CAC, while hiding original protected primary inputs among decoy primary inputs. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0. Our experiments show that CAC 2.0 is resilient to existing SAT-based, removal, and structural analysis attacks. To achieve this, it increases the number of key inputs at most 4x and the gate-level area between 30.2% and 0.8% on circuits with low and high complexity with respect to CAC.

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks

TL;DR

This paper tackles the vulnerability of existing logic locking to structural analysis by introducing CAC 2.0, an enhanced multi-flip locking approach. CAC 2.0 combines Double CAC with obfuscation of protected primary inputs to massively expand the attack surface a structural-analysis adversary must explore, while maintaining resilience to SAT-based and removal attacks. The authors implement CAC 2.0 and other techniques in the open-source HIID tool, demonstrate substantial, circuit-dependent hardware overhead, and show empirical resilience against a broad set of OL and OG attacks. The work provides a practical, auditable path to stronger IP protection in RTL pipelines, with clear trade-offs between security gain and area/power impact.

Abstract

Logic locking proposed to protect integrated circuits from serious hardware threats has been studied extensively over a decade. In these years, many efficient logic locking techniques have been proven to be broken. The state-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks, but vulnerable to structural analysis attacks. To overcome this drawback, this paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. To do so, CAC 2.0 locks the original circuit twice, one after another, on different nodes with different number of protected primary inputs using CAC, while hiding original protected primary inputs among decoy primary inputs. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0. Our experiments show that CAC 2.0 is resilient to existing SAT-based, removal, and structural analysis attacks. To achieve this, it increases the number of key inputs at most 4x and the gate-level area between 30.2% and 0.8% on circuits with low and high complexity with respect to CAC.
Paper Structure (13 sections, 5 figures, 4 tables)

This paper contains 13 sections, 5 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Logic Locking
  4. Defenses
  5. Attacks
  6. Proposed Logic Locking Technique and Tool
  7. CAC 2.0: Proposed Logic Locking Technique
  8. Double CAC
  9. Obfuscation of Protected Primary Inputs
  10. HIID: Proposed Logic Locking Tool
  11. Experimental Results
  12. Conclusions
  13. Acknowledgment

Figures (5)

  • Figure 1: Conventional logic locking in the IC design flow.
  • Figure 2: State-of-the-art logic locking techniques aksoy24: (a) SFLT; (b) DFLT.
  • Figure 3: Techniques to overcome the vulnerability of CAC to structural analysis attacks: (a) double CAC; (b) obfuscation of protected primary inputs.
  • Figure 4: Impact of the number of key inputs on the hardware complexity in CAC 2.0: (a) area; (b) delay; (c) power dissipation.
  • Figure 5: Impact of the number of key inputs on the number of iterations and run-time of the SAT-based attack in CAC 2.0.