Hiding Information for Secure and Covert Data Storage in Commercial ReRAM Chips

TL;DR

This work presents a low-cost, hardware-modification-free scheme to hide data in commercial ReRAM by encoding information into the analog set/reset timing ($t_{Set,256}$ and $t_{Reset,256}$) of stressed cells. By selecting a secret set of addresses and repeatedly stressing them to create distinguishable timing differences, secret bits are embedded without altering normal memory content, and retrieved through timing analysis and a threshold or clustering approach. The approach is demonstrated on five MB85AS8MT ReRAM chips, achieving encoding at about $0.4$ bit/min and retrieval at about $15.625$ bits/s, with robustness to temperature and aging and tolerable endurance costs. Security is enhanced by using a hiding key, replication, and rotation or cipher-based address selection, making unauthorized retrieval difficult even under post-hiding stress, while still offering practical applications in covert data storage and robust watermarking.

Abstract

This article introduces a novel, low-cost technique for hiding data in commercially available resistive-RAM (ReRAM) chips. The data is kept hidden in ReRAM cells by manipulating its analog physical properties through switching ($\textit{set/reset}$) operations. This hidden data, later, is retrieved by sensing the changes in cells' physical properties (i.e., $\textit{set/reset}$ time of the memory cells). The proposed system-level hiding technique does not affect the normal memory operations and does not require any hardware modifications. Furthermore, the proposed hiding approach is robust against temperature variations and the aging of the devices through normal read/write operation. The silicon results show that our proposed data hiding technique is acceptably fast with ${\sim}0.4bit/min$ of encoding and ${\sim}15.625bits/s$ of retrieval rates, and the hidden message is unrecoverable without the knowledge of the secret key, which is used to enhance the security of hidden information.

Figures (16)

• Figure 1: ReRAM cell structure with two logic states ReRAM_Mao.
• Figure 2: Operation steps used to hide information.
• Figure 3: ReRAM cell characterization under stress- (a) $t_{Set,256}$ and (b) $t_{Reset,256}$.
• Figure 4: Influence of replica size on the hidden information, using- (a) $t_{Set,[32,256]}$, and (b) $t_{Reset,[32,256]}$.
• Figure 5: Retention characteristics of the hidden information using $t_{Set,256}$.