Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms

TL;DR

This work addresses accurate delay modeling in block-based SSTA by deriving an exact PDF for gate delays when inputs are Gaussian and correlated, revealing a non-Gaussian delay distribution that results from the max operation. By representing non-Gaussian delays as Gaussian mixtures and leveraging a closed-form convolution with the gate-time distribution, the authors enable exact delay propagation through timing graphs via GaKeDA, a Gaussian Kernel Density Estimation-based algorithm. They provide closed-form expressions for the gate-delay PDF, its first two moments (mean and standard deviation), and higher moments, along with a linear-programming approach to fit Gaussian mixtures efficiently. The proposed Gaussian-comb framework and LP-based optimization yield a scalable, accurate alternative to MC, with performance guarantees and applicability to practical SSTA on large designs. This advances precise, fast timing verification under realistic parameter variations and correlations.

Abstract

In this paper, the Statistical Static Timing Analysis (SSTA) is considered within the block--based approach. The statistical model of the logic gate delay propagation is systematically studied and the exact analytical solution is obtained, which is strongly non-Gaussian. The procedure of handling such (non-Gaussian) distributions is described and the corresponding algorithm for the critical path delay is outlined. Finally, the proposed approach is tested and compared with Monte Carlo simulations.

Figures (15)

• Figure 1: Combinational Logic Circuit modelling in Static Timing Analysis. A simple logic circuit on the left, and its timing graph in the middle and on the right. The timing graph can be traversed either within block-based or path-based approach.
• Figure 2: An example combinational circuit with a symbolic notation of logic gates and interconnects. The timing graph is split in a levelised manner (blocks), which indicates the block--based analysis.
• Figure 3: Illustration of delay propagation through a logic gate. At stage (a), two signals arrive at the input of the gate. At stage (b), the $\max$-operation is performed, which gives a skewed PDF. At the same time, the gate has its own operation time described by some distribution (c). Thus, the distribution of the gate delay (d) requires the convolution of the obtained distribution (b) and given (c). This convolution results in a new distribution, which clearly has a non-Gaussian form.
• Figure 4: High-level illustration of the decomposition of a non-Gaussian function and its representation by means of a sum of Radial Basis Functions.
• Figure 5: Comparison of different expressions for the PDF of the maximum of two Gaussian RVs, $X_1\sim\mathcal{N}(1,0.5)$ and $X_2\sim\mathcal{N}(3,3)$ for different correlation coefficients $\rho$. The blue line shows the exact expression \ref{['chap5:eq:max_2_correlated']}, the orange line shows the linear-in-$\rho$ expression \ref{['chap5:eq:max_2_corr_weak']}, and the dashed black line corresponds to the independent case \ref{['chap2:eq:max_2_independent']}. For the purpose of illustration, $X_1$ and $X_2$ in this example are two Gaussian RVs with different $\mu$ and $\sigma$.