Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge

TL;DR

Spiker+ tackles the challenge of enabling efficient edge inference with Spiking Neural Networks by delivering a complete FPGA-focused framework that automatically generates configurable, low-power accelerators. The approach combines a hierarchical hardware architecture (Network, Layer, Neuron), six neuron variants, a Python-based configuration flow, surrogate-gradient training compatibility, and a VHDL generator, producing ready-to-deploy cores on Xilinx boards. Empirical results on MNIST and SHD show strong area and power efficiency (e.g., MNIST at 180 mW and 780 μs per image; SHD at 430 mW and 54 μs) with competitive accuracies (93.85% and 72.99%, respectively), underscoring the practicality of frugal SNNs for edge devices. The work advances hardware-accelerated neuromorphic computing by offering an end-to-end, configurable toolchain that optimizes accuracy, latency, and energy under tight resource constraints and is released as open-source for community development.

Abstract

Including Artificial Neural Networks in embedded systems at the edge allows applications to exploit Artificial Intelligence capabilities directly within devices operating at the network periphery. This paper introduces Spiker+, a comprehensive framework for generating efficient, low-power, and low-area customized Spiking Neural Networks (SNN) accelerators on FPGA for inference at the edge. Spiker+ presents a configurable multi-layer hardware SNN, a library of highly efficient neuron architectures, and a design framework, enabling the development of complex neural network accelerators with few lines of Python code. Spiker+ is tested on two benchmark datasets, the MNIST and the Spiking Heidelberg Digits (SHD). On the MNIST, it demonstrates competitive performance compared to state-of-the-art SNN accelerators. It outperforms them in terms of resource allocation, with a requirement of 7,612 logic cells and 18 Block RAMs (BRAMs), which makes it fit in very small FPGA, and power consumption, draining only 180mW for a complete inference on an input image. The latency is comparable to the ones observed in the state-of-the-art, with 780us/img. To the authors' knowledge, Spiker+ is the first SNN accelerator tested on the SHD. In this case, the accelerator requires 18,268 logic cells and 51 BRAM, with an overall power consumption of 430mW and a latency of 54 us for a complete inference on input data. This underscores the significance of Spiker+ in the hardware-accelerated SNN landscape, making it an excellent solution to deploy configurable and tunable SNN architectures in resource and power-constrained edge applications.

Figures (10)

• Figure 1: Typical architectures of an
• Figure 2: Landscape of neuromorphic hardware
• Figure 3: Spiker+ example of architecture. The example includes three layers with different numbers of neurons and depicts all the architecture's main control blocks.
• Figure 4: Internal architecture of the Network and Layer
• Figure 5: Spiker+ neuron architectures in order of increasing complexity from left to right (, I-order and II-order ), with the subtractive reset on top and the fixed one on the bottom. In the multiplexers, channels labeled with I indicate the beginning of the Integrate path, R the beginning of the Reset path, and L the beginning of the Leakage path.