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Darwin3: A large-scale neuromorphic chip with a Novel ISA and On-Chip Learning

De Ma, Xiaofei Jin, Shichun Sun, Yitao Li, Xundong Wu, Youneng Hu, Fangchao Yang, Huajin Tang, Xiaolei Zhu, Peng Lin, Gang Pan

TL;DR

Darwin3 introduces a domain-specific ISA and a connectivity compression mechanism to enable large-scale neuromorphic hardware tailored for spiking neural networks. The 24×24 NoC-based chip, with a central RISC-V controller and neuron cores that support up to 2.35 million neurons, achieves dramatic improvements in code density and synaptic capacity through a flexible topology representation. Experimental results show competitive accuracy and latency in inference, plus robust on-chip learning capabilities, while energy efficiency is enhanced by asynchronous interconnects and power-down memories. The work demonstrates two million-neuron-scale applications, including a spiking VGG-16 ensemble and a maze-solving SNN, highlighting Darwin3’s potential to scale neuromorphic systems with high efficiency and adaptability for CSNNs. Overall, Darwin3 advances hardware-software co-design for SNNs by combining a compact, expressive ISA with a highly compressed, scalable connectivity framework.

Abstract

Spiking Neural Networks (SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture(ISA), which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to 2.35 million neurons, making it the largest of its kind in neuron scale. The experimental results showed that code density was improved up to 28.3x in Darwin3, and neuron core fan-in and fan-out were improved up to 4096x and 3072x by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8X and 200.8X when mapping convolutional spiking neural networks (CSNN) onto the chip, demonstrating state-of-the-art performance in accuracy and latency compared to other neuromorphic chips.

Darwin3: A large-scale neuromorphic chip with a Novel ISA and On-Chip Learning

TL;DR

Darwin3 introduces a domain-specific ISA and a connectivity compression mechanism to enable large-scale neuromorphic hardware tailored for spiking neural networks. The 24×24 NoC-based chip, with a central RISC-V controller and neuron cores that support up to 2.35 million neurons, achieves dramatic improvements in code density and synaptic capacity through a flexible topology representation. Experimental results show competitive accuracy and latency in inference, plus robust on-chip learning capabilities, while energy efficiency is enhanced by asynchronous interconnects and power-down memories. The work demonstrates two million-neuron-scale applications, including a spiking VGG-16 ensemble and a maze-solving SNN, highlighting Darwin3’s potential to scale neuromorphic systems with high efficiency and adaptability for CSNNs. Overall, Darwin3 advances hardware-software co-design for SNNs by combining a compact, expressive ISA with a highly compressed, scalable connectivity framework.

Abstract

Spiking Neural Networks (SNNs) are gaining increasing attention for their biological plausibility and potential for improved computational efficiency. To match the high spatial-temporal dynamics in SNNs, neuromorphic chips are highly desired to execute SNNs in hardware-based neuron and synapse circuits directly. This paper presents a large-scale neuromorphic chip named Darwin3 with a novel instruction set architecture(ISA), which comprises 10 primary instructions and a few extended instructions. It supports flexible neuron model programming and local learning rule designs. The Darwin3 chip architecture is designed in a mesh of computing nodes with an innovative routing algorithm. We used a compression mechanism to represent synaptic connections, significantly reducing memory usage. The Darwin3 chip supports up to 2.35 million neurons, making it the largest of its kind in neuron scale. The experimental results showed that code density was improved up to 28.3x in Darwin3, and neuron core fan-in and fan-out were improved up to 4096x and 3072x by connection compression compared to the physical memory depth. Our Darwin3 chip also provided memory saving between 6.8X and 200.8X when mapping convolutional spiking neural networks (CSNN) onto the chip, demonstrating state-of-the-art performance in accuracy and latency compared to other neuromorphic chips.
Paper Structure (19 sections, 7 equations, 5 figures, 6 tables)

This paper contains 19 sections, 7 equations, 5 figures, 6 tables.

Table of Contents

  1. INTRODUCTION
  2. THE DARWIN3 DOMAIN-SPECIFIC ISA
  3. Model Abstraction of Neurons, Synapses, and Learning
  4. The Proposed Darwin3 ISA
  5. THE DARWIN3 CHIP ARCHITECTURE
  6. Overview
  7. Architecture of Neuron Cores
  8. Representation of Neuronal Connections
  9. EXPERIMENTAL RESULTS
  10. Comparison with The State-of-the-Art Neuromorphic Chips
  11. Neuron Number
  12. Synapse Capacity
  13. Code Density
  14. Inference and Learning Performance
  15. Energy Efficiency
  16. ...and 4 more sections

Figures (5)

  • Figure 1: Typical Data Path. (a) The Data Path of $v_{adp}$. (b) The Data Path of $v_{m}$. (c) The Data Path of $w$. (d) The Common Data Path for State Variables.
  • Figure 2: The Architecture of The Chip Top and Main Blocks. (a) The Top Architecture of The Proposed Chip. (b) The Architecture of a Neuron Core. (c) The Architecture for Inference and Learning Process. (d) The Architecture of The Synapses.
  • Figure 3: The Test Chip and System Board
  • Figure 4: Comparison of Code Density and Memory Usage. (a) Comparison of Required Weight Memory Across Typical Networks. (b) Comparison of Code Density.
  • Figure 5: Two Large-scale Applications with A Million of Neurons. (a) Spiking VGG-16 Ensembling. (b) Directly-trained SNN-based Maze Solving.