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Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET

Yifei Zhou, Xuchu Huang, Jianyi Yang, Kai Ni, Hussam Amrouch, Cheng Zhuo, Xunzhao Yin

TL;DR

This work tackles the temperature sensitivity problem in subthreshold FeFET-based compute-in-memory (CiM) designs, which aim to minimize power for edge AI. It introduces a 2T-1FeFET cell with a feedback ring between two subthreshold MOSFETs to suppress temperature drift, enabling reliable MAC operations from 0 to 85 ℃. Validation on a VGG network for CIFAR-10 shows 89.45% accuracy, with an energy efficiency of 2866 TOPS/W and per-MAC energy around 3.14 fJ, while maintaining non-overlapping outputs across mac outputs. The proposed approach offers a practical path to ultra-low-power, temperature-resilient CiM suitable for energy-constrained AI/IoT devices.

Abstract

Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as 'memory wall' issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION/IOFF ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0 to 85 Celsius, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T-1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W.

Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET

TL;DR

This work tackles the temperature sensitivity problem in subthreshold FeFET-based compute-in-memory (CiM) designs, which aim to minimize power for edge AI. It introduces a 2T-1FeFET cell with a feedback ring between two subthreshold MOSFETs to suppress temperature drift, enabling reliable MAC operations from 0 to 85 ℃. Validation on a VGG network for CIFAR-10 shows 89.45% accuracy, with an energy efficiency of 2866 TOPS/W and per-MAC energy around 3.14 fJ, while maintaining non-overlapping outputs across mac outputs. The proposed approach offers a practical path to ultra-low-power, temperature-resilient CiM suitable for energy-constrained AI/IoT devices.

Abstract

Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as 'memory wall' issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION/IOFF ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0 to 85 Celsius, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T-1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W.
Paper Structure (12 sections, 3 equations, 9 figures, 2 tables)

This paper contains 12 sections, 3 equations, 9 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background
  3. FeFET Basics
  4. Subthreshold Computing Design
  5. Subthreshold Operation vs. Temperature Resilience
  6. Proposed Temperature-resilient 2T-1FeFET CiM Design
  7. Temperature Drift on Existing Designs
  8. Proposed 2T-1FeFET Design
  9. Validation and Evaluation
  10. Temperature Resilience Validation
  11. Performance Evaluation
  12. Conclusion

Figures (9)

  • Figure 1: FeFET structure and characteristic line at different temperatures and at two states (low-$V_{TH}$/high-$V_{TH}$). FeFETs working under the chosen $V_{read}=0.35V$ in our design are fully lying in the subthreshold region.
  • Figure 2: The traditional 8-bit wordlength 1FeFET-1R structureSoliman_2020.
  • Figure 3: Output current of 1FeFET-1R cell at temperatures from 0℃ to 85℃ under the same input voltages and normalized output current with reference temperature at 27℃. (a) $V_{read}=1.3V$ (saturation region, which is the operating voltage of Soliman_2020). (b) $V_{read}=0.35V$ (subthreshold region). Current fluctuation is measured by the difference of nominal output current to 1.
  • Figure 4: Output voltage ranges at temperatures from 0℃ to 85℃ of an 1FeFET-1R CiM array with 8 cells per row. MAC outputs are from 0 to 8 and overlap with each other, causing computation errors.
  • Figure 5: Schematic of the proposed 2T-1FeFET cell design for CiM array, with the feedback loop for temperature drift compensation.
  • ...and 4 more figures