Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang
TL;DR
This work tackles the challenge of automatically extracting symmetry constraints in analog circuit layouts to accelerate design cycles. It introduces an edge-augmented graph attention network (EGAT) that processes directed netlist graphs with detailed node and edge features, enabling robust device-level symmetry detection. The framework combines a directed graph representation, rich feature design, and post-processing rules to dramatically improve accuracy and F1 scores over state-of-the-art baselines, achieving near-perfect performance on OTA circuits and strong results on Hybrid circuits. The approach reduces manual labeling, scales to complex circuits, and has potential to streamline analog layout workflows in practice.
Abstract
In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices' information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F1-score.