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When Memory Mappings Attack: On the (Mis)use of the ARM Cortex-M FPB Unit

Haoqi Shan, Dean Sullivan, Orlando Arias

TL;DR

This work addresses how memory-mapped design-for-debug interfaces, notably the Flash Patch and Breakpoint (FPB) unit in Cortex-M MCUs, can undermine embedded security by enabling persistence and data leakage without a debug probe. The authors develop FPB-based attack primitives, demonstrate their feasibility across multiple Cortex-M cores, and show they can bypass MPU protections and disrupt RTOS isolation, challenging commonly deployed defenses. Key contributions include a practical FPB exploitation framework, baseline and real-world demonstrations, and a discussion of existing defenses and their vulnerabilities, underscoring the need to re-evaluate the security implications of debug features in modern microcontrollers. The work highlights a significant practical risk in widely deployed devices and advocates balancing debug functionality with robust security controls to prevent on-chip debugging interfaces from becoming attack surfaces.

Abstract

In recent years we have seen an explosion in the usage of low-cost, low-power microcontrollers (MCUs) in embedded devices around us due to the popularity of Internet of Things (IoT) devices. Although this is good from an economics perspective, it has also been detrimental for security as microcontroller-based systems are now a viable attack target. In response, researchers have developed various protection mechanisms dedicated to improve security in these resource-constrained embedded systems. We demonstrate in this paper these defenses fall short when we leverage benign memory mapped design-for-debug (DfD) structures added by MCU vendors in their products. In particular, we utilize the Flash Patch and Breakpoint (FPB) unit present in the ARM Cortex-M family to build new attack primitives which can be used to bypass common defenses for embedded devices. Our work serves as a warning and a call in balancing security and debug structures in modern microcontrollers.

When Memory Mappings Attack: On the (Mis)use of the ARM Cortex-M FPB Unit

TL;DR

This work addresses how memory-mapped design-for-debug interfaces, notably the Flash Patch and Breakpoint (FPB) unit in Cortex-M MCUs, can undermine embedded security by enabling persistence and data leakage without a debug probe. The authors develop FPB-based attack primitives, demonstrate their feasibility across multiple Cortex-M cores, and show they can bypass MPU protections and disrupt RTOS isolation, challenging commonly deployed defenses. Key contributions include a practical FPB exploitation framework, baseline and real-world demonstrations, and a discussion of existing defenses and their vulnerabilities, underscoring the need to re-evaluate the security implications of debug features in modern microcontrollers. The work highlights a significant practical risk in widely deployed devices and advocates balancing debug functionality with robust security controls to prevent on-chip debugging interfaces from becoming attack surfaces.

Abstract

In recent years we have seen an explosion in the usage of low-cost, low-power microcontrollers (MCUs) in embedded devices around us due to the popularity of Internet of Things (IoT) devices. Although this is good from an economics perspective, it has also been detrimental for security as microcontroller-based systems are now a viable attack target. In response, researchers have developed various protection mechanisms dedicated to improve security in these resource-constrained embedded systems. We demonstrate in this paper these defenses fall short when we leverage benign memory mapped design-for-debug (DfD) structures added by MCU vendors in their products. In particular, we utilize the Flash Patch and Breakpoint (FPB) unit present in the ARM Cortex-M family to build new attack primitives which can be used to bypass common defenses for embedded devices. Our work serves as a warning and a call in balancing security and debug structures in modern microcontrollers.
Paper Structure (19 sections, 2 figures, 1 table)

This paper contains 19 sections, 2 figures, 1 table.

Figures (2)

  • Figure 1: Setting up the FPB to intercept (a) instruction fetches, and (b) data fetches.
  • Figure 2: FPB setup for arbitrary code execution in privileged mode. In this example, after our code executes, the MPU is completely disabled on the system. For simplicity, we chose to place the data literal at the end of the instruction sequence.