Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks

TL;DR

A graph neural network (GNN)-based machine learning model is proposed for rapid and accurate cell library characterization and a fine-grained drive strength interpolation methodology is proposed to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.

Abstract

Design technology co-optimization (DTCO) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTCO flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners and technology parameters. Validation with 512 unseen technology corners and over one million test data points shows accurate predictions of delay, power, and input pin capacitance for 33 types of cells, with a mean absolute percentage error (MAPE) $\le$ 0.95% and a speed-up of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error $\le$3.0 ps for WNS, percentage errors $\le$0.60% for leakage power, and $\le$0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.

Figures (6)

• Figure 1: Cell library serves as the bridge between process development and performance evaluations of the system-level DTCO iterations.
• Figure 2: The structure of our fast cell library characterization method: from dataset generation to design performance evaluation. ① represents the cell characterization process for dataset generation; ② describes the model training and implementation process.
• Figure 3: Distribution of training and testing corners for 45nm silicon technology (left) and flexible technology (right).
• Figure 4: Prediction comparison between our proposed model and reference model in 45nm silicon technology about cell delay.
• Figure 5: Histograms of $R^{2}$ score of capacitance (left) and cell delay prediction (right).