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Reducing strain fluctuations in quantum dot devices by gate-layer stacking

Collin C. D. Frink, Talise Oh, E. S. Joseph, Merritt P. Losert, E. R. MacQuarrie, Benjamin D. Woods, M. A. Eriksson, Mark Friesen

TL;DR

The paper addresses strain fluctuations in gate-defined Si/SiGe quantum dots that can hinder qubit uniformity. Using orthotropic elasticity and 3D simulations across simple to realistic gate geometries, it identifies two regimes—gate-driven and oxide-driven—whose competing signs allow strategic design to suppress short-range strain fluctuations. The authors demonstrate that gate-layer stacking, with carefully tuned oxide and global-gate thicknesses, can nearly eliminate these fluctuations (with up to ~3x suppression in overlapping-gate devices), though long-range effects remain and may require electrostatic compensation. This strain-engineering framework offers practical guidelines for scalable, uniform quantum-dot qubit arrays in semiconductor quantum computing.

Abstract

Nanofabricated metal gate electrodes are commonly used to confine and control electrons in electrostatically defined quantum dots. However, these same gates impart strain-induced potential fluctuations that can potentially impair device functionality. Here we investigate strain fluctuations in Si/SiGe heterostructures, caused by (i) lattice mismatch, (ii) materials-dependent thermal contraction, and (iii) depositional stress in the metal gates. By simulating gate geometries, ranging from simple to realistically complicated, we identify two opposing effects in overlapping gate structures: (a) gate-driven behavior arising from isolated gates vs (b) oxide-driven behavior arising from the thin oxides separating the gates in an overlapping geometry. These limiting behaviors induce strains of opposite sign, pointing towards the possibility of suppressing strain fluctuations through careful design. Here, we demonstrate nearly total suppression of short-range strain fluctuation through device optimization. These results suggest that strain fluctuations should not pose an insurmountable challenge to qubit uniformity, provided that oxide and overlapping gate thicknesses can be tuned.

Reducing strain fluctuations in quantum dot devices by gate-layer stacking

TL;DR

The paper addresses strain fluctuations in gate-defined Si/SiGe quantum dots that can hinder qubit uniformity. Using orthotropic elasticity and 3D simulations across simple to realistic gate geometries, it identifies two regimes—gate-driven and oxide-driven—whose competing signs allow strategic design to suppress short-range strain fluctuations. The authors demonstrate that gate-layer stacking, with carefully tuned oxide and global-gate thicknesses, can nearly eliminate these fluctuations (with up to ~3x suppression in overlapping-gate devices), though long-range effects remain and may require electrostatic compensation. This strain-engineering framework offers practical guidelines for scalable, uniform quantum-dot qubit arrays in semiconductor quantum computing.

Abstract

Nanofabricated metal gate electrodes are commonly used to confine and control electrons in electrostatically defined quantum dots. However, these same gates impart strain-induced potential fluctuations that can potentially impair device functionality. Here we investigate strain fluctuations in Si/SiGe heterostructures, caused by (i) lattice mismatch, (ii) materials-dependent thermal contraction, and (iii) depositional stress in the metal gates. By simulating gate geometries, ranging from simple to realistically complicated, we identify two opposing effects in overlapping gate structures: (a) gate-driven behavior arising from isolated gates vs (b) oxide-driven behavior arising from the thin oxides separating the gates in an overlapping geometry. These limiting behaviors induce strains of opposite sign, pointing towards the possibility of suppressing strain fluctuations through careful design. Here, we demonstrate nearly total suppression of short-range strain fluctuation through device optimization. These results suggest that strain fluctuations should not pose an insurmountable challenge to qubit uniformity, provided that oxide and overlapping gate thicknesses can be tuned.
Paper Structure (10 sections, 9 equations, 14 figures, 3 tables)

This paper contains 10 sections, 9 equations, 14 figures, 3 tables.

Figures (14)

  • Figure 1: Schematic illustration of the suppression of strain fluctuations by gate-layer stacking. a Non-uniform strain in a Si/SiGe quantum well (blue/green) is induced beneath a metal wire (light gray) upon cooling the device, due to differing thermal expansion coefficients in the materials. The red line indicates the plane of the two-dimensional electron gas (2DEG). b Same as a, with a global gate covering the original wire. If the oxide layer (dark gray) between the gates is thin enough, and the overlapping gate is thick enough, the combined structure imparts a nearly uniform strain field to the quantum well below. For thinner structures, oxide and gate thicknesses can be carefully tuned to yield similar uniformity. Note that strains and structural deformations have been exaggerated in these diagrams, for visual clarity; see simulations, below, for numerically accurate results.
  • Figure 2: Strain simulations of a single-wire geometry. a,b 3D and cross-sectional views, respectively, with the coordinate axes indicated. From bottom to top, the thicknesses of the Si$_{0.7}$Ge$_{0.3}$ virtual substrate (green), Si quantum well (blue), Si$_{0.7}$Ge$_{0.3}$ spacer (green), and insulating Al$_2$O$_3$ layer (dark gray) are 2 $\mu$m, 9 nm, 40 nm, and 10 nm, respectively. A metal wire (light gray) of height 60 nm and variable width $w$ is formed of Al or Pd. The wire is covered on the top and sides by a thin 2 nm Al$_2$O$_3$ layer (dark gray; not shown in a, for clarity). All strain and energy fluctuations in this work are evaluated on the horizontal red line in b, corresponding to the plane of the 2DEG, which is taken to lie 1.5 nm below the top quantum-well interface. cThe diagonal components of the strain tensor, $\varepsilon_{xx}$, $\varepsilon_{yy}$, and $\varepsilon_{zz}$ are shown for the case of a single Al wire of width $w = 80$ nm.d,e Corresponding conduction-band energy offsets $\Delta E_c$, for Al (d) or Pd (e) wires of width $w=80$ nm (shaded region), with depositional stresses as indicated. We also assume thermal contractions appropriate for a temperature of 1 K, as described in Methods. The peak-to-peak width $w^*$ and amplitude $A$ of the fluctuations are defined in d. f,g Results for $w^*$ and $A$ are plotted as a function of the actual wire width $w$. The dashed line in f corresponds to $w^* = w$. Closed triangles in g correspond to Al wires, following the color scheme in d, while open circles correspond to Pd, following the color scheme in e. Insets show energy shifts orthogonal to the wire, for the indicated Pd wire parameters.
  • Figure 3: Strain simulations of a parallel-wire geometry, with and without a large ($18\times 18$$\mu$m$^2$) global gate of variable thickness $t_g$, fabricated on the same heterostructure as Fig. \ref{['FIG_SingleWire']}. (Figures are not to scale.) a A cross-sectional view of five parallel Al wires (80 nm wide, 70 nm tall, with 40 nm gaps between them). The wires are separated from the global gate by a layer of Al$_2$O$_3$ with variable thickness, $t_\text{ox}$. b A 3D depiction of the same geometry. In both a and b, the topmost 2 nm oxide layer is not shown, for clarity. c Conduction-band energy modulations $\Delta E_c$, for the geometry depicted in a,b, with varying $t_g$ values and $t_\text{ox}=2$ nm. d Same as c, but with a $t_\text{ox}=7$ nm. c,d Dashed black lines show results for a global gate of thickness $t_g=700$ nm, which is ten times greater than the height of the five wires. The results are very similar to those from a much thinner global gate (solid black lines), with the same thickness as the five wires, $t_g=70$ nm. The gray lines show results for the case of no global gate, $t_g=0$. The blue and pink lines show results for the optimized geometries that minimize fluctuations, corresponding to $t_g=28.5$ nm in c and $t_g=11.5$ nm in d.
  • Figure 4: Strain simulations of the two-dot device of Xue2021, for two configurations of stacked Al gates, and two oxide thicknesses. From bottom to top, the thicknesses of the Si$_{0.7}$Ge$_{0.3}$ virtual substrate, Si quantum well, Si$_{0.7}$Ge$_{0.3}$ spacer, and Si cap are 1.2 $\mu$m, 8 nm, 30 nm, and 1 nm, respectively. a Reduced gate set, including only the lower layer of gates (20 nm thick), is shown in red. We also include Al$_2$O$_3$ layers of variable thickness, above and below the lower gate layer (top oxide layer is not shown, for clarity). b Same as a, but including a global top gate (turquoise) of thickness 40 nm. c,d Strain-induced fluctuations of $\Delta E_c$ in the plane of the 2DEG, for the geometries shown in a and b, respectively, where all oxide layers have a thickness of 2 nm. e,f Same as c and d, except the oxide layers have a thickness of 7 nm. In c-f, approximate dot locations are indicated by green stars, and we have shifted the energy scale such that $\Delta E_c=0$ at the dot centers. g Horizontal linecuts, indicated in panels c-f, with appropriate color codings. We again highlight a key result: the linecut most closely associated with gate-driven behavior (solid--purple line) exhibits fluctuations with opposite sign as the linecut most associated with oxide-driven behavior (dashed-black line).h Vertical linecuts, indicated in panels d and f, with appropriate color codings.
  • Figure 5: Strain simulations of the quadruple-dot device of Ref. Neyens2019, for several configurations of stacked Al gates fabricated on the same heterostructure as Fig. \ref{['FIG_SingleWire']}. a A reduced gate set, including only screening gates (maroon, $30~\text{nm}$ thick), plunger gates (blue, $50~\text{nm}$ thick), and upper reservoir gates (also shown in blue because they are formed in the same layer as the plungers). b The full gate geometry, including the gate layers in a, as well as side-reservoir gates (also blue), and tunnel-barrier gates (yellow, $70~\text{nm}$ thick). Two additional gate configurations are considered in Supplementary Fig. \ref{['FIG_Quad_Grid']}. Note that every gate layer is covered by 2 nm of Al$_2$O$_3$, although the topmost layer is not pictured, for clarity. c, d Strain-induced fluctuations of $\Delta E_c$ in the plane of the 2DEG, for the geometries shown in a and b, respectively. e Results for the horizontal linecuts indicated in c (dot-dashed gray line) and d (solid black line), which pass through the centers of the lower four dots. f Results for the vertical linecuts indicated in d. Note the emergence of a strain-induced double-well potential.
  • ...and 9 more figures