Improving Parameter Training for VQEs by Sequential Hamiltonian Assembly

TL;DR

This work tackles vanishing gradients in parameterized quantum circuits by introducing Sequential Hamiltonian Assembly (SHA), which builds the global loss from local Hamiltonian components via iterative assembly. The method is evaluated on Graph Coloring with a VQE, showing substantial gains in mean accuracy over standard VQE and Layer-VQE, and is analyzed alongside related layerwise approaches. SHA leverages problem-informed, locality-aware decompositions of the cost function to ease optimization and mitigate barren plateaus, with potential applicability to a wide class of combinatorial problems. The findings suggest that locality-aware training can significantly improve PQC trainability, albeit with higher training time, and point to fruitful future directions including broader problem domains and hybrid combinations with existing learning strategies.

Abstract

A central challenge in quantum machine learning is the design and training of parameterized quantum circuits (PQCs). Similar to deep learning, vanishing gradients pose immense problems in the trainability of PQCs, which have been shown to arise from a multitude of sources. One such cause are non-local loss functions, that demand the measurement of a large subset of involved qubits. To facilitate the parameter training for quantum applications using global loss functions, we propose a Sequential Hamiltonian Assembly, which iteratively approximates the loss function using local components. Aiming for a prove of principle, we evaluate our approach using Graph Coloring problem with a Varational Quantum Eigensolver (VQE). Simulation results show, that our approach outperforms conventional parameter training by 29.99% and the empirical state of the art, Layerwise Learning, by 5.12% in the mean accuracy. This paves the way towards locality-aware learning techniques, allowing to evade vanishing gradients for a large class of practically relevant problems.

Figures (4)

• Figure 1: Accuracy over all graphs and circuit architectures per used assembly strategy.
• Figure 2: Solution quality averaged over all graphs and circuit architectures for all considered approaches.
• Figure 3: Solution quality averaged over all graphs and circuit architectures when combining different approaches.
• Figure 4: Number of optimization iterations.