On-sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design

TL;DR

This work proposes the design of fully customized ADCs and presents, for the first time, a co-design framework for generating bespoke Decision Tree classifiers and shows that the co- design enables self-powered operation of on-sensor printed classifiers in all benchmark cases.

Abstract

Printed electronics (PE) technology provides cost-effective hardware with unmet customization, due to their low non-recurring engineering and fabrication costs. PE exhibit features such as flexibility, stretchability, porosity, and conformality, which make them a prominent candidate for enabling ubiquitous computing. Still, the large feature sizes in PE limit the realization of complex printed circuits, such as machine learning classifiers, especially when processing sensor inputs is necessary, mainly due to the costly analog-to-digital converters (ADCs). To this end, we propose the design of fully customized ADCs and present, for the first time, a co-design framework for generating bespoke Decision Tree classifiers. Our comprehensive evaluation shows that our co-design enables self-powered operation of on-sensor printed classifiers in all benchmark cases.

Figures (5)

• Figure 1: Schematic of: a) conventional 3-bit Flash ADC and b) an example of an equivalent bespoke ADC with four unary digits of output.
• Figure 2: Illustration of how a conventional Decision Tree (a) is translated into unary format, represented by a set of unary digits. This example assumes Q0.4 formatted values, e.g., $0.75\rightarrow6$. (b) depicts the simplified schematic.
• Figure 3: The Area and power of (4-bit) bespoke ADCs w.r.t. their output unary digits. The first values correspond to 1-output ADCs, while the last one to 15-output ADC. Different points denote different output digits. Selected output digits are in sequential order, i.e., "$U_1$-$U_2$" 2-$U_D$ ADC is followed by "$U_2$-$U_3$" 2-$U_D$ ADC and so on, only to showcase the behavior of power.
• Figure 4: Total area and power reduction (x) compared to the baseline designs Mubarik:MICRO:2020:printedml (i.e., vs Table \ref{['tab:baselines']}). For our printed Decision Trees only our proposed bespoke ADCs and parallel unary architecture are considered.
• Figure 5: Evaluation of the additional hardware gains delivered by our ADC-aware training. Total area and power reductions (%) of our printed DTs w/ and w/o our ADC-aware training are compared (i.e., vs Fig. \ref{['fig:adconly']}). Three accuracy loss constraints are considered: a) 0% (i.e., no accuracy loss), b) 1%, c) 5%.